公开(公告)号：WO2014078333A2

公开(公告)日：2014-05-22

申请号：PCT/US2013069752

申请日：2013-11-12

Applicant: QUALCOMM INC

Inventor： TASIC ALEKSANDAR MIODRAG ,  DAVIERWALLA ANOSH BOMI ,  NARATHONG CHIEWCHARN ,  VAN ZALINGE KLAAS

IPC: H03F3/193

CPC classification number: H04W88/02 ,  H03F3/193 ,  H03F3/68 ,  H04B1/0053

Abstract: Omni-band amplifiers supporting multiple band groups are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes at least one gain transistor and a plurality of cascode transistors for a plurality of band groups. Each band group covers a plurality of bands. The gain transistor(s) receive an input radio frequency (RF) signal. The cascode transistors are coupled to the gain transistor(s) and provide an output RF signal for one of the plurality of band groups. In an exemplary design, the gain transistor(s) include a plurality of gain transistors for the plurality of band groups. One gain transistor and one cascode transistor are enabled to amplify the input RF signal and provide the output RF signal for the selected band group. The gain transistors may be coupled to different taps of a single source degeneration inductor or to different source degeneration inductors.

Abstract translation: 公开了支持多频带组的全频带放大器。 在示例性设计中，装置（例如，无线设备，集成电路等）包括用于多个频带组的至少一个增益晶体管和多个级联晶体管。 每个乐队组涵盖多个乐队。 增益晶体管接收输入射频（RF）信号。 级联晶体管耦合到增益晶体管并为多个频带组中的一个提供输出RF信号。 在示例性设计中，增益晶体管包括用于多个频带组的多个增益晶体管。 一个增益晶体管和一个共源共栅晶体管能够放大输入RF信号并为选定的频带组提供输出RF信号。 增益晶体管可以耦合到单个源极退化电感器的不同抽头或不同源极退化电感器。

公开(公告)号：WO2008014282A2

公开(公告)日：2008-01-31

申请号：PCT/US2007074257

申请日：2007-07-24

Applicant: QUALCOMM INC ,  NARATHONG CHIEWCHARN ,  SU WENJUN

Inventor： NARATHONG CHIEWCHARN ,  SU WENJUN

IPC: H01M8/10

CPC classification number: H03K23/667 ,  H03K21/10 ,  H03L7/1976

Abstract: A multi-modulus divider (MMD) receives an MMD input signal and outputs an MMD output signal SOUT. The MMD includes a chain of modulus divider stages (MDSs). Each MDS receives an input signal, divides it by either two or three, and outputs the result as an output signal. Each MDS responds to its own modulus control signal that controls whether it divides by two or three. In one example, a sequential logic element outputs SOUT. The low jitter modulus control signal of one of the first MDS stages of the chain is used to place a sequential logic element into a first state. The output signal of one of the MDS stages in the middle of the chain is used to place the sequential logic element into a second state. Power consumption is low because the sequential logic element is not clocked at the high frequency of the MMD input signal.

Abstract translation: 多模式分频器（MMD）接收MMD输入信号并输出​​MMD输出信号SOUT。 MMD包括模数分频器级链（MDS）。 每个MDS接收一个输入信号，将其分为两个或三个，并输出结果作为输出信号。 每个MDS响应自己的模数控制信号，控制它是否被二或三除。 在一个示例中，顺序逻辑元件输出SOUT。 链的第一MDS级之一的低抖动模数控制信号用于将顺序逻辑元件置于第一状态。 链中间的MDS级之一的输出信号用于将顺序逻辑元件置于第二状态。 功耗很低，因为顺序逻辑元件不在MMD输入信号的高频时钟。

公开(公告)号：WO2014204706A3

公开(公告)日：2015-03-19

申请号：PCT/US2014041641

申请日：2014-06-10

Applicant: QUALCOMM INC

Inventor： LIU LI ,  NARATHONG CHIEWCHARN

IPC: H04B1/00 ,  H04B1/40 ,  H04W16/14 ,  H04W72/02 ,  H04W88/06

CPC classification number: H04W88/06 ,  H04B1/0053 ,  H04B1/403 ,  H04W16/14 ,  H04W72/1215

Abstract: A wireless device supporting concurrent communication with multiple wireless systems of different radio access technologies (RATs) are disclosed. In an exemplary design, an apparatus includes first and second receivers supporting concurrent signal reception from wireless systems of different RATs. The first receiver receives a first downlink signal from a first wireless system of a first RAT. The second receiver receives a second downlink signal from a second wireless system of a second RAT, which is different from the first RAT. The first and second receivers may operate concurrently. The second receiver may be broadband and/or may support carrier aggregation. The apparatus may further include first and second local oscillator (LO) generators to generate LO signals for the first and second receivers, respectively, based on different divider ratios in order to mitigate voltage controlled oscillator (VCO) pulling.

Abstract translation: 公开了一种支持与不同无线电接入技术（RAT）的多个无线系统的并发通信的无线设备。 在示例性设计中，装置包括支持来自不同RAT的无线系统的并发信号接收的第一和第二接收机。 第一接收机从第一RAT的第一无线系统接收第一下行链路信号。 第二接收机从与第一RAT不同的第二RAT的第二无线系统接收第二下行链路信号。 第一和第二接收器可以同时运行。 第二接收机可以是宽带和/或可以支持载波聚合。 该装置还可以包括第一和第二本地振荡器（LO）发生器，以分别基于不同的分频器比率产生用于第一和第二接收机的LO信号，以便减轻压控振荡器（VCO）的拉动。

公开(公告)号：WO2012048036A3

公开(公告)日：2012-08-02

申请号：PCT/US2011054974

申请日：2011-10-05

Applicant: QUALCOMM INC ,  LIU LI ,  NARATHONG CHIEWCHARN ,  GUDEM PRASAD SRINIVASA SIVA

Inventor： LIU LI ,  NARATHONG CHIEWCHARN ,  GUDEM PRASAD SRINIVASA SIVA

IPC: H03D3/24 ,  H03L7/093 ,  H04B1/00 ,  H04B1/40 ,  H04W88/06

CPC classification number: H03L7/1976 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03L7/093 ,  H03L7/099 ,  H03L7/104 ,  H04B1/0057

Abstract: A transceiver for multi-standard operation (usable, for example, to communicate signals both of a first wireless communication standard and of a second wireless communication standard) has a mixer that receives a local oscillator signal generated by a local oscillator. A PLL of the local oscillator involves a VCO, a digitally programmable analog loop filter, a digitally programmable VCO supply voltage circuit, and a digitally programmable VCO varactor bias control circuit. In one aspect, the bandwidth of the analog loop filter is adjusted depending on the communication standard of the signal being communicated. In other aspects, the VCO supply voltage circuit and/or the varactor bias control circuit are configured in different ways to optimize PLL performance depending on the communication standard of the signal being communicated.

Abstract translation: 用于多标准操作的收发器（例如可用于传送第一无线通信标准和第二无线通信标准的信号）具有接收由本地振荡器产生的本地振荡器信号的混合器。 本地振荡器的PLL包括VCO，数字可编程模拟环路滤波器，数字可编程VCO电源电压电路和数字可编程VCO变容二极管偏置控制电路。 在一个方面，模拟环路滤波器的带宽根据正在传送的信号的通信标准来调节。 在其他方面，VCO电源电压电路和/或变容二极管偏置控制电路以不同的方式配置，以根据正在通信的信号的通信标准优化PLL性能。

公开(公告)号：WO2015047951A2

公开(公告)日：2015-04-02

申请号：PCT/US2014056792

申请日：2014-09-22

Applicant: QUALCOMM INC

Inventor： RANGARAJAN RAJAGOPALAN ,  TRIKHA PUSHP KUMAR ,  NARATHONG CHIEWCHARN

IPC: H04L5/00

CPC classification number: H04W48/18 ,  H04B1/406 ,  H04L5/001 ,  H04L27/2647

Abstract: Certain aspects of the present disclosure provide methods and apparatus for dynamically secondary cell (SCELL) allocation and frequency planning for carrier aggregation. One example system for radio frequency (RF) signal processing, generally includes a first integrated circuit (IC) comprising two or more receive chains, each receive chain for processing one of multiple component carriers in a carrier aggregation (CA) signal, wherein the first IC is configured to downconvert a signal associated with a primary cell of the CA signal; and a second IC configured to downconvert one or more signals associated with one or more secondary cells of the CA signal. The second IC may also be configured to upconvert a signal having a frequency different than the primary cell by an offset associated with the primary cell.

Abstract translation: 本公开的某些方面提供了用于载波聚合的动态辅小区（SCELL）分配和频率规划的方法和装置。 用于射频（RF）信号处理的一个示例系统通常包括包含两个或更多个接收链的第一集成电路（IC），每个接收链用于处理载波聚合（CA）信号中的多个分量载波中的一个，其中第一 IC被配置为下变频与CA信号的主小区相关联的信号; 以及第二IC，被配置为下变频与CA信号的一个或多个辅助小区相关联的一个或多个信号。 第二IC还可以被配置为将具有与主小区不同的频率的信号上变频与主小区相关联的偏移。

公开(公告)号：WO2010068504A3

公开(公告)日：2010-08-19

申请号：PCT/US2009065962

申请日：2009-11-25

Applicant: QUALCOMM INC ,  ANIRUDDHAN SANKARAN ,  NARATHONG CHIEWCHARN ,  SRIDHARA RAVI ,  NEJATI BABAK

Inventor： ANIRUDDHAN SANKARAN ,  NARATHONG CHIEWCHARN ,  SRIDHARA RAVI ,  NEJATI BABAK

IPC: H03C3/40 ,  H03C5/00 ,  H04L27/36

CPC classification number: H03C5/00 ,  H03C3/40 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1483 ,  H03D7/1491 ,  H03D7/165 ,  H03D7/166 ,  H03D2200/0023 ,  H03D2200/0084 ,  H03G3/3042 ,  H04L27/34 ,  H04L27/36 ,  H04L27/361 ,  H04L27/362 ,  H04L27/38 ,  H04L27/389

Abstract: Method and apparatus for configuring a transmitter circuit to support linear or polar mode. In the linear mode, a baseband signal is specified by adjusting the amplitudes of in-phase (I) and quadrature (Q) signals, while in the polar mode, the information signal is specified by adjusting the phase of a local oscillator (LO) signal and the amplitude of either an I or a Q signal. In an exemplary embodiment, two mixers are provided for both linear and polar mode, with a set of switches selecting the appropriate input signals provided to one of the mixers based on whether the device is operating in linear or polar mode. In an exemplary embodiment, each mixer may be implemented using a scalable architecture that efficiently adjusts mixer size based on required transmit power.

Abstract translation: 用于配置发射机电路以支持线性或极性模式的方法和设备。 在线性模式中，通过调整同相（I）和正交（Q）信号的幅度来指定基带信号，而在极性模式中，通过调整本地振荡器（LO）的相位来指定信息信号， 信号和I或Q信号的幅度。 在示例性实施例中，为线性模式和极性模式提供两个混频器，其中一组开关基于设备是以线性还是极性模式工作来选择提供给混频器之一的适当输入信号。 在示例性实施例中，可以使用基于所需发射功率有效地调整混频器大小的可扩展架构来实现每个混频器。

公开(公告)号：WO2008002792A2

公开(公告)日：2008-01-03

申请号：PCT/US2007071496

申请日：2007-06-18

Applicant: QUALCOMM INC ,  NARATHONG CHIEWCHARN ,  SU WENJUN

Inventor： NARATHONG CHIEWCHARN ,  SU WENJUN

CPC classification number: H03K19/01721 ,  H03K3/356017 ,  H03K19/018514

Abstract: Differential signal output nodes of a novel CML buffer are DC-coupled by contiguous conductors to the differential signal input nodes of a load (for example, a CML logic element). The CML buffer includes a pulldown load latch that increases buffer transconductance and that provides a DC bias voltage across the conductors and onto the input nodes of the load, thereby obviating the need for the load to have DC biasing circuitry. Capacitors of a conventional AC coupling between buffer and load are not needed, thereby reducing the amount of die area needed to realize the circuit and thereby reducing the capacitance of the buffer-to-load connections. Switching power consumption is low due to the low capacitance buffer-to-load connections. Differential signals can be communicated from buffer to load over a wide frequency range of from less than five kilohertz to more than one gigahertz with less than fifty percent signal attenuation.

Abstract translation: 新型CML缓冲器的差分信号输出节点通过连续的导体直接耦合到负载的差分信号输入节点（例如，CML逻辑元件）。 CML缓冲器包括下拉负载锁存器，其增加缓冲器跨导，并且在导体和负载的输入节点之间提供DC偏置电压，从而避免了负载需要DC偏置电路。 不需要在缓冲器和负载之间的常规AC耦合的电容器，从而减少实现电路所需的管芯面积，从而减小缓冲器到负载连接的电容。 由于低电容缓冲器到负载连接，开关功耗很低。 差分信号可以从小于五千赫到宽达一千兆赫的宽频率范围内从缓冲器传送到负载，信号衰减小于百分之五十。

公开(公告)号：WO2006110907A2

公开(公告)日：2006-10-19

申请号：PCT/US2006014175

申请日：2006-04-11

Applicant: QUALCOMM INC ,  FLORESCU OCTAVIAN ,  FAHIM AMR M ,  NARATHONG CHIEWCHARN

Inventor： FLORESCU OCTAVIAN ,  FAHIM AMR M ,  NARATHONG CHIEWCHARN

IPC: H03L7/10 ,  H03L7/093

CPC classification number: H03L7/199 ,  H03L7/0898 ,  H03L7/10

Abstract: A PLL includes a charge pump, a loop filter, a VCO, and a calibration unit. The calibration unit performs coarse tuning to select one or multiple frequency ranges, performs fine tuning to determine an initial control voltage that puts the VCO near a desired operating frequency, measures the VCO gain at different control voltages, and derives VCO gain compensation values for the different control voltages. The calibration unit also pre-charges the loop filter to the initial control voltage to shorten acquisition time, enables the loop filter to drive the VCO to lock to the desired operating frequency, and performs VCO gain compensation during normal operation. For VCO gain compensation, the calibration unit measures the control voltage, obtains the VCO gain compensation value for the measured control voltage, and adjusts the gain of at least one circuit block (e.g., the charge pump) to account for variation in the VCO gain.

Abstract translation: PLL包括电荷泵，环路滤波器，VCO和校准单元。 校准单元执行粗调以选择一个或多个频率范围，执行微调以确定将VCO置于所需工作频率附近的初始控制电压，测量不同控制电压下的VCO增益，并导出VCO增益补偿值 不同的控制电压。 校准单元还将环路滤波器预充电到初始控制电压以缩短采集时间，使环路滤波器能够驱动VCO锁定到所需的工作频率，并在正常操作期间执行VCO增益补偿。 对于VCO增益补偿，校准单元测量控制电压，获得测量的控制电压的VCO增益补偿值，并调整至少一个电路块（例如，电荷泵）的增益，以考虑VCO增益的变化 。

公开(公告)号：WO2014093409A3

公开(公告)日：2014-08-28

申请号：PCT/US2013074221

申请日：2013-12-10

Applicant: QUALCOMM INC

Inventor： LEUNG LAI KAN ,  NARATHONG CHIEWCHARN ,  HU JIANYUN ,  FENG YUNFEI

IPC: H04B17/00 ,  H04B1/30

CPC classification number: H04B17/21 ,  H04B1/16 ,  H04B1/30 ,  H04B17/00 ,  H04B17/29

Abstract: Receiver circuits that can be reconfigured to generate test signals in a wireless device are disclosed. In an exemplary design, an apparatus includes a mixer and an amplifier. The mixer downconverts an input radio frequency (RF) signal based on a local oscillator (LO) signal in a first mode. The amplifier, which is formed by at least a portion of the mixer, amplifies the LO signal and provides an amplified LO signal in a second mode. In another exemplary design, an apparatus includes an amplifier and an attenuator. The amplifier receives and amplifies an input RF signal in a first mode. The attenuator, which is formed by at least a portion of the amplifier, receives and passes an LO signal in a second mode.

Abstract translation: 公开了可以重新配置为在无线设备中生成测试信号的接收器电路。 在示例性设计中，装置包括混频器和放大器。 混频器在第一模式中基于本地振荡器（LO）信号来下变频输入射频（RF）信号。 由混频器的至少一部分形成的放大器放大LO信号并在第二模式下提供放大的LO信号。 在另一个示例性设计中，装置包括放大器和衰减器。 放大器在第一模式下接收并放大输入RF信号。 由放大器的至少一部分形成的衰减器以第二模式接收并通过LO信号。

公开(公告)号：WO2012048034A3

公开(公告)日：2012-07-05

申请号：PCT/US2011054971

申请日：2011-10-05

Applicant: QUALCOMM INC ,  LIU LI ,  NARATHONG CHIEWCHARN

Inventor： LIU LI ,  NARATHONG CHIEWCHARN

IPC: H03B5/12 ,  H03L1/02

CPC classification number: H03L1/025 ,  H03B5/04 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03L1/023 ,  H03L7/099 ,  H03L7/104 ,  H03L7/1976

Abstract: A resonator of a VCO includes a fine tuning main varactor circuit, an auxiliary varactor circuit, and a coarse tuning capacitor bank circuit coupled in parallel with an inductance. The main varactor circuit includes a plurality of circuit portions that can be separately disabled. Within each circuit portion is a multiplexing circuit that supplies a selectable one of either a fine tuning control signal (FTAVCS) or a temperature compensation control signal (TCAVCS) onto a varactor control node within the circuit portion. If the circuit portion is enabled then the FTAVCS is supplied onto the control node so that the circuit portion is used for fine tuning. If the circuit portion is disabled then the TCAVCS is supplied onto the control node so that the circuit portion is used to combat VCO frequency drift as a function of temperature. How the voltage of the TCAVCS varies with temperature is digitally programmable.

Abstract translation: VCO的谐振器包括微调主变容二极管电路，辅助变容二极管电路和与电感并联耦合的粗调电容器组电路。 主变容二极管包括多个电路部分，其可以单独禁用。 在每个电路部分内是多路复用电路，其将微调控制信号（FTAVCS）或温度补偿控制信号（TCAVCS）中的可选择的一个提供到电路部分内的变容二极管控制节点上。 如果电路部分被使能，则FTAVCS被提供到控制节点上，使得电路部分被用于微调。 如果电路部分被禁用，则TCAVCS被提供到控制节点上，使得电路部分用于抵抗作为温度的函数的VCO频率漂移。 TCAVCS的电压如何随温度而变化是可数字编程的。