公开(公告)号：AU2003251575A8

公开(公告)日：2003-12-31

申请号：AU2003251575

申请日：2003-06-18

Applicant: QUALCOMM INC

Inventor： LAI KING CHUNG ,  SIH GILBERT CHRISTOPHER ,  MAURO ANTHONY PATRICK II ,  CHANG CHIENCHUNG

IPC: H04N7/32 ,  G06T9/00 ,  H04N7/26 ,  H04N7/50

Abstract: This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.

公开(公告)号：AU2003251575A1

公开(公告)日：2003-12-31

申请号：AU2003251575

申请日：2003-06-18

Applicant: QUALCOMM INC

Inventor： LAI KING CHUNG ,  SIH GILBERT CHRISTOPHER ,  CHANG CHIENCHUNG ,  MAURO ANTHONY PATRICK II

IPC: H04N7/32 ,  G06T9/00 ,  H04N7/26 ,  H04N7/50

Abstract: This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.

公开(公告)号：WO03030391A3

公开(公告)日：2003-08-28

申请号：PCT/US0231776

申请日：2002-10-02

Applicant: QUALCOMM INC

Inventor： CHALLA RAGHU ,  SIH GILBERT CHRISTOPHER ,  GLAZKO SERGUEI A

IPC: H04B1/7075 ,  H04B1/708 ,  H04B1/7087 ,  H04B1/7117 ,  H04B1/707

CPC classification number: H04B1/708 ,  H04B1/70753 ,  H04B1/7087 ,  H04B1/7117 ,  H04B2201/70701 ,  H04B2201/70707

Abstract: Techniques to acquire pilots over code space and/or frequency errors. In one aspect, pilot acquisition is performed using a number of substages, and some of the substages are pipelined and performed in parallel using different processing elements. A searcher initially searches over a designated code space to find peaks, and these peaks may be re-evaluated. Finger processors then attempt to acquire the candidate peaks. The searcher may be operated to search for the next set of peaks while the finger processors process the current set of peaks. In another aspect, the full range of frequency errors for the pilots is divided into a number of frequency bins. A multi-stage scheme is used to evaluate the bins, and may employ pipelining and parallel processing such that a search for peaks in the next bin is performed while acquisition of peaks found for the current bin is attempted.

Abstract translation: 在代码空间和/或频率误差上获取导频的技术。 在一个方面，使用多个子站执行导频采集，并且使用不同的处理单元并行地执行一些子级。 搜索者最初搜索指定的代码空间以找到峰值，并且可以重新评估这些峰值。 然后，手指处理器尝试获取候选峰。 当手指处理器处理当前的峰值集合时，搜索器可以被操作以搜索下一组峰值。 在另一方面，导频的全部频率误差范围被分成多个频率仓。 使用多级方案来评估箱，并且可以采用流水线和并行处理，使得在尝试对当前箱找到的峰的采集期间执行下一箱中的峰的搜索。

公开(公告)号：WO03107681A2

公开(公告)日：2003-12-24

申请号：PCT/US0319401

申请日：2003-06-18

Applicant: QUALCOMM INC

Inventor： LAI KING-CHUNG ,  SIH GILBERT CHRISTOPHER ,  CHANG CHIENCHUNG ,  MAURO II ANTHONY PATRICK

IPC: H03M7/36 ,  H04N19/156 ,  H04N19/43 ,  H04N19/51 ,  H04N7/26 ,  H04N7/50

CPC classification number: H04N19/43 ,  H04N19/51 ,  H04N19/61

Abstract: This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.

Abstract translation: 本公开描述了能够减少编码视频序列所需的处理周期数量和存储器传输的视频编码技术。 以这种方式，所公开的视频编码技术可以增加视频编码速度并降低功耗。 通常，视频编码技术利用将视频块存储在与用于运动估计例程的搜索空间相对应的列中的候选存储器。 存储器控制单元寻址候选存储器以并行检索多个像素，以便与要编码的视频块中的像素同时比较，例如使用绝对差值（SAD）或平方和差（SSD）技术。 差分处理器执行并行计算。 此外，对于要编码的后续视频块，可以通过加载新的视频块列来递增地更新候选存储器，而不是重新加载整个搜索空间。

公开(公告)号：WO2005101213A3

公开(公告)日：2006-01-26

申请号：PCT/US2005008373

申请日：2005-03-11

Applicant: QUALCOMM INC ,  SIH GILBERT CHRISTOPHER ,  SAKAMAKI CHARLES E ,  HSU DE D ,  WEI JIAN ,  HIGGINS RICHARD

Inventor： SIH GILBERT CHRISTOPHER ,  SAKAMAKI CHARLES E ,  HSU DE D ,  WEI JIAN ,  HIGGINS RICHARD

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/08 ,  G06F12/0857 ,  G06F12/0897 ,  G06F2212/251 ,  G06F2212/253

Abstract: A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

Abstract translation: 描述了可以处理高速率输入数据并确保嵌入式DSP能够满足实时约束的高速缓存存储器系统。 缓存的存储器系统包括位于处理器核心附近的高速缓存存储器，处于下一较高存储器级别的片上存储器以及最高存储器级别的外部主存储器。 缓存控制器处理高速缓冲存储器和片上存储器之间的指令和数据的分页用于高速缓存未命中。 直接存储交换（DME）控制器处理片上存储器和外部存储器之间的用户控制的寻呼。 用户/程序员可以安排在处理器核心实际需要之前将处理器核心所需的指令和数据存储在片上存储器中。