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公开(公告)号：CA2438333C
公开(公告)日：2011-11-01
申请号：CA2438333
申请日：2002-02-15
Applicant: QUALCOMM INC
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INYUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT CHRISTOPHER
Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
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公开(公告)号：BRPI0509082A
公开(公告)日：2007-08-21
申请号：BRPI0509082
申请日：2005-03-11
Applicant: QUALCOMM INC
Inventor： SIH GILBERT CHRISTOPHER , SAKAMAKI CHARLES E , HSU DE D , WEI JIAN , HIGGINS RICHARD
IPC: G06F12/08
Abstract: A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.
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公开(公告)号：BR0213089A
公开(公告)日：2004-12-28
申请号：BR0213089
申请日：2002-10-02
Applicant: QUALCOMM INC
Inventor： CHALLA RAGHU , SIH GILBERT CHRISTOPHER , GLAZKO SERGUEI A
IPC: H04B1/7075 , H04B1/708 , H04B1/7087 , H04B1/7117 , H04B1/707
Abstract: Techniques to acquire pilots over code space and/or frequency errors. In one aspect, pilot acquisition is performed using a number of substages, and some of the substages are pipelined and performed in parallel using different processing elements. A searcher initially searches over a designated code space to find peaks, and these peaks may be re-evaluated. Finger processors then attempt to acquire the candidate peaks. The searcher may be operated to search for the next set of peaks while the finger processors process the current set of peaks. In another aspect, the full range of frequency errors for the pilots is divided into a number of frequency bins. A multi-stage scheme is used to evaluate the bins, and may employ pipelining and parallel processing such that a search for peaks in the next bin is performed while acquisition of peaks found for the current bin is attempted.
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公开(公告)号：AU2003238295A1
公开(公告)日：2003-12-31
申请号：AU2003238295
申请日：2003-06-18
Applicant: QUALCOMM INC
Abstract: This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.
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公开(公告)号：AU2003238295A8
公开(公告)日：2003-12-31
申请号：AU2003238295
申请日：2003-06-18
Applicant: QUALCOMM INC
Abstract: This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.
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Patent Agency Ranking
公开(公告)号：AU2003214154A1
公开(公告)日：2003-09-29
申请号：AU2003214154
申请日：2003-03-12
Applicant: QUALCOMM INC
Inventor： SIH GILBERT CHRISTOPHER , ABRISHAMKAR FARROKH , RICK ROLAND
Abstract: The velocity of a wireless communications device (WCD) is estimated. In response to this estimated velocity, a tracking speed of a filter is determined that corresponds to the estimated velocity. The filter filters a timing error signal to produce a control signal that controls the timing of a synchronization clock. This synchronization clock may be a finger clock that controls the timing of a pseudonoise (PN) sequence generator configured for despreading a pilot symbol sequence.
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公开(公告)号：AU2003213824A1
公开(公告)日：2003-09-29
申请号：AU2003213824
申请日：2003-03-11
Applicant: QUALCOMM INC
Inventor： EKVETCHAVIT THUNYACHATE , SIH GILBERT CHRISTOPHER , PATEL SHIMMAN
Abstract: The velocity of a wireless communications device (WCD) (106) is estimated. In response to this estimate a power control command rate is determined. The WCD 106 transmits power control signals to a base station (102) according to the power control command rate. The power control command rate may be determined by mapping the estimated velocity to a velocity range, and selecting a rate that corresponds to the velocity range as the power control command rate. Velocity is estimated by measuring a level crossing rate of a multipath signal.
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公开(公告)号：CA2479013A1
公开(公告)日：2003-09-25
申请号：CA2479013
申请日：2003-03-11
Applicant: QUALCOMM INC
Inventor： PATEL SHIMMAN , EKVETCHAVIT THUNYACHATE , SIH GILBERT CHRISTOPHER
Abstract: The velocity of a wireless communications device (WCD) (106) is estimated. I n response to this estimate a power control command rate is determined. The WC D 106 transmits power control signals to a base station (102) according to the power control command rate. The power control command rate may be determined by mapping the estimated velocity to a velocity range, and selecting a rate that corresponds to the velocity range as the power control command rate. Velocity is estimated by measuring a level crossing rate of a multipath sign al.
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公开(公告)号：SG151304A1
公开(公告)日：2009-04-30
申请号：SG2009020108
申请日：2005-03-11
Applicant: QUALCOMM INC
Inventor： SIH GILBERT CHRISTOPHER , SAKAMAKI CHARLES E , HSU DE D , WEI JIAN , HIGGINS RICHARD
IPC: G06F12/08
Abstract: CACHED MEMORY SYSTEM AND CACHE CONTROLLER FOR EMBEDDED DIGITAL SIGNAL PROCESSOR A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.
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公开(公告)号：BR0308331A
公开(公告)日：2005-04-05
申请号：BR0308331
申请日：2003-03-12
Applicant: QUALCOMM INC
Inventor： SIH GILBERT CHRISTOPHER , ABRISHAMKAR FARROKH , RICK ROLAND
IPC: H04B1/707
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