公开(公告)号：WO2009079468A2

公开(公告)日：2009-06-25

申请号：PCT/US2008086856

申请日：2008-12-15

Applicant: QUALCOMM INC ,  SUN BO ,  ANIRUDDHAN SANKARAN

Inventor： SUN BO ,  ANIRUDDHAN SANKARAN

IPC: H03F1/02 ,  H03F1/32 ,  H03F3/19 ,  H03F3/24 ,  H03F3/30 ,  H03G3/20 ,  H03G3/30

CPC classification number: H03F3/3022 ,  H03F1/0272 ,  H03F1/301 ,  H03F1/308 ,  H03F1/3217 ,  H03F3/19 ,  H03F3/245 ,  H03F2200/102 ,  H03F2200/435 ,  H03F2200/451 ,  H03F2200/78 ,  H03F2200/99 ,  H03F2203/30015 ,  H03F2203/30027 ,  H03F2203/30061 ,  H03F2203/30147 ,  H03F2203/30153 ,  H03G1/007 ,  H03G3/3042

Abstract: Techniques are provided for dynamically biasing an amplifier to extend the amplifier's operating range while conserving power. In an embodiment, a detector is provided to measure the amplifier output to determine an operating region of the amplifier. The output of the detector may be input to a bias adjuster, which outputs a dynamic voltage level supplied to at least one bias transistor in the amplifier. Multiple embodiments of the detector and bias adjuster are disclosed.

Abstract translation: 提供了技术来动态地偏置放大器以延长放大器的工作范围，同时节省功率。 在一个实施例中，提供检测器来测量放大器输出以确定放大器的工作区域。 检测器的输出可以被输入到偏置调节器，偏置调节器输出提供给放大器中的至少一个偏置晶体管的动态电压电平。 公开了检测器和偏置调节器的多个实施例。

公开(公告)号：WO2004068700A2

公开(公告)日：2004-08-12

申请号：PCT/US2004001642

申请日：2004-01-21

Applicant: QUALCOMM INC ,  SUN BO

Inventor： SUN BO

IPC: H03F1/26 ,  H03F1/32 ,  H03F3/68 ,  H03F

CPC classification number: H03F1/26 ,  H03F1/32 ,  H03F1/3223 ,  H03F3/68 ,  H03F2200/294 ,  H03F2200/372

Abstract: A feedforward nonlinearity cancellation scheme is used to improve the linearity of a low noise amplifier (LNA). An LNA incorporates a main amplifier and an auxiliary amplifier couple to receive the same input. The outputs of the main amplifier and the auxiliary amplifier are also coupled. The auxiliary amplifier may be implemented as a very low power auxiliary amplifier having a very low linearity. The output of the auxiliary amplifier contains third-order intermodulation (IM3) products that are of similar amplitude, but opposite phase, to the IM3 products generated by the main amplifier. With the outputs of the main amplifier and the auxiliary amplifier coupled, their respective IM3 products are summed together and effectively cancel each other out. As a result, the output of the LNA contains substantially no IM3 products, and the linearity of the LNA is substantially improved.

Abstract translation: 前馈非线性消除方案用于提高低噪声放大器（LNA）的线性度。 LNA集成了主放大器和辅助放大器耦合，以接收相同的输入。 主放大器和辅助放大器的输出也耦合。 辅助放大器可以被实现为具有非常低线性度的极低功率辅助放大器。 辅助放大器的输出包含与主放大器产生的IM3产品具有相似幅度但相反相位的三阶互调（IM3）产品。 随着主放大器和辅助放大器的输出耦合，它们各自的IM3产品相加在一起，并有效地相互抵消。 结果，LNA的输出基本上不含有IM3产物，并且LNA的线性度显着提高。

公开(公告)号：WO2014150707A3

公开(公告)日：2015-07-23

申请号：PCT/US2014024035

申请日：2014-03-12

Applicant: QUALCOMM INC

Inventor： TANG YI ,  SUN BO

IPC: G04F10/00 ,  H03L7/08

CPC classification number: H03M1/50 ,  G04F10/005 ,  H03L7/08 ,  H03L7/0991 ,  H03L2207/50

Abstract: A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.

Abstract translation: 时间 - 数字转换器将参考时钟信号和振荡信号的转换时间之间的差异转换成数值信号，其数值信号与转换时序差成比例。 该时间 - 数字转换器包括边缘检测器，时间 - 电压转换器和模 - 数转换器。 边缘检测器适于在参考时钟信号的每个周期期间检测最靠近参考时钟信号的边缘的振荡信号的边沿（跃迁）。 时间 - 电压转换器适于产生与所检测的振荡信号的边沿与基准时钟信号的边沿之间的时间差成比例的模拟信号。 模拟 - 数字转换器适于将模拟信号转换成数字信号，该数字信号的值与振荡信号的检测到的边沿的出现与参考时钟信号的边沿之间的差成比例。

公开(公告)号：WO2009152105A3

公开(公告)日：2010-04-01

申请号：PCT/US2009046642

申请日：2009-06-08

Applicant: QUALCOMM INC ,  SUN BO ,  BALLANTYNE GARY JOHN ,  RANGARAJAN RAJAGOPALAN

Inventor： SUN BO ,  BALLANTYNE GARY JOHN ,  RANGARAJAN RAJAGOPALAN

IPC: H03L7/099 ,  H03B5/12 ,  H04B1/04 ,  H04B1/16

CPC classification number: H03L7/099 ,  H03L2207/06

Abstract: Techniques for calibrating digitally controlled oscillators (DCOs) are disclosed. In an aspect of the disclosure, an initial set of control codes for operating the DCO is determined. A range of output frequencies produced from the initial set is identified. Gaps or instances of overlap are identified in the frequency range. For the overlap case, control codes are removed from the initial set that correspond to the overlap instance to establish a revised set. For the gap case, control codes are added to the initial set for producing frequencies values that fill the gap. An apparatus for performing the same is also disclosed.

Abstract translation: 公开了用于校准数字控制振荡器（DCO）的技术。 在本公开的一方面，确定用于操作DCO的初始控制代码集。 识别从初始集合产生的输出频率范围。 在频率范围内识别重叠的间隙或实例。 对于重叠情况，从与重叠实例相对应的初始集中移除控制代码以建立修订集。 对于间隙情况，将控制代码添加到初始设置中，以产生填充间隙的频率值。 还公开了一种用于执行该装置的装置。

公开(公告)号：WO2009073580A3

公开(公告)日：2010-01-07

申请号：PCT/US2008085084

申请日：2008-11-29

Applicant: QUALCOMM INC ,  BALLANTYNE GARY JOHN ,  SUN BO

Inventor： BALLANTYNE GARY JOHN ,  SUN BO

IPC: H03L7/085

CPC classification number: H03L7/10 ,  H03L7/085 ,  H03L7/087 ,  H03L2207/50

Abstract: In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping tracking of the number of oscillator signal cycles based on the reference signal.

Abstract translation: 在一个方面，数字PLL（DPLL）基于输入和输出相位的小数部分进行操作。 DPLL累加至少一个输入信号以获得输入相位。 DPLL基于来自振荡器的振荡器信号与参考信号之间的相位差（例如使用时间 - 数字转换器（TDC））来确定输出相位的小数部分。 DPLL根据输入相位的小数部分和输出相位的小数部分确定相位误差。 DPLL然后基于相位误差产生振荡器的控制信号。 在另一方面，DPLL包括合成的累加器，其通过基于参考信号跟踪振荡器信号周期的数量来确定粗略的输出相位。

公开(公告)号：WO2009055622A2

公开(公告)日：2009-04-30

申请号：PCT/US2008081033

申请日：2008-10-23

Applicant: QUALCOMM INC ,  SUN BO ,  SAHOTA GURKANWAL SINGH ,  WU YUE

Inventor： SUN BO ,  SAHOTA GURKANWAL SINGH ,  WU YUE

IPC: H03L7/10 ,  H03L7/08 ,  H03L7/093 ,  H03L7/107

CPC classification number: H03L7/197 ,  H03J7/065 ,  H03L1/00 ,  H03L7/0802 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/107 ,  H03L2207/06

Abstract: A local oscillator includes a phase-locked loop. The phase-locked loop includes voltage controlled oscillator (VCO) and a novel VCO control circuit. The VCO control circuit may be programmable and configurable. In one example, an instruction is received onto the VCO control circuit to change the power state of the VCO. The instruction is issued by other circuitry in response to a detected change in RF channel conditions (for example, a change in a signal-to-noise determination) in a cellular telephone. In response, the VCO control circuit outputs control signals that gradually widen the loop bandwidth of the PLL, then gradually change the VCO bias current to change the VCO power state, and then narrow the loop bandwidth of the PLL back to its original bandwidth. The entire process of widening the PLL bandwidth, changing the VCO power state, and narrowing the PLL bandwidth occurs while the PLL remains locked.

Abstract translation: 本地振荡器包括锁相环。 锁相环包括压控振荡器（VCO）和新型VCO控制电路。 VCO控制电路可以是可编程和可配置的。 在一个示例中，在VCO控制电路上接收指令以改变VCO的功率状态。 响应于在蜂窝电话中的RF信道条件（例如，信噪比确定的改变）检测到的变化，由其它电路发出指令。 作为响应，VCO控制电路输出逐渐拓宽PLL环路带宽的控制信号，然后逐渐改变VCO偏置电流，改变VCO功率状态，然后将PLL的环路带宽缩小回原来的带宽。 当PLL保持锁定时，会发生整个PLL带宽扩大，改变VCO功率状态和缩小PLL带宽的过程。