公开(公告)号：JP2013062845A

公开(公告)日：2013-04-04

申请号：JP2012242672

申请日：2012-11-02

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： SUN BO ,  GURKANWAL SINGH SAHOTA ,  WU YUE

IPC: H03L7/099

CPC classification number: H03L7/197 ,  H03J7/065 ,  H03L1/00 ,  H03L7/0802 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/107 ,  H03L2207/06

Abstract: PROBLEM TO BE SOLVED: To provide a local oscillator in radio communication equipment.SOLUTION: A local oscillator includes a phase-locked loop. The phase-locked loop includes a voltage controlled oscillator 23 and a novel VCO control circuit 27. The VCO control circuit may be programmable and configurable. In one example, an instruction is received onto the VCO control circuit to change the power state of the VCO. The instruction is issued by other circuitry in response to a detected change in radio channel conditions (for example, a change in a signal-to-noise determination) in a cellular telephone. In response, the VCO control circuit outputs control signals that gradually widen the loop bandwidth of the PLL, then gradually change the VCO bias current to change the VCO power state, and then narrow the loop bandwidth of the PLL back to its original bandwidth. The entire process of widening the PLL bandwidth, changing the VCO power state, and narrowing the PLL bandwidth occurs while the PLL remains locked.

Abstract translation: 要解决的问题：在无线电通信设备中提供本地振荡器。 解决方案：本地振荡器包括锁相环。 锁相环包括压控振荡器23和新型的VCO控制电路27. VCO控制电路可以是可编程的和可配置的。 在一个示例中，在VCO控制电路上接收指令以改变VCO的功率状态。 响应于蜂窝电话中的无线电信道条件（例如，信噪比确定的改变）的检测到的改变，由其他电路发出指令。 作为响应，VCO控制电路输出逐渐拓宽PLL环路带宽的控制信号，然后逐渐改变VCO偏置电流，改变VCO功率状态，然后将PLL的环路带宽缩小回原来的带宽。 当PLL保持锁定时，会发生整个PLL带宽扩大，改变VCO功率状态和缩小PLL带宽的过程。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012257269A

公开(公告)日：2012-12-27

申请号：JP2012158980

申请日：2012-07-17

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： GARY JOHN BALLANTYNE ,  SUN BO

IPC: H03L7/06 ,  H03L7/085

CPC classification number: H03L7/10 ,  H03L7/085 ,  H03L7/087 ,  H03L2207/50

Abstract: PROBLEM TO BE SOLVED: To provide a digital PLL (DPLL) operating based on fractional portions of input and output phases.SOLUTION: The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase on the basis of a phase difference between an oscillator signal from an oscillator and a reference signal, for example, using a time-to-digital converter (TDC). The DPLL determines a phase error on the basis of the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator on the basis of the phase error. In another aspect, a DPLL including a synthesized accumulator determines a coarse output phase by keeping tracking of the number of oscillator signal cycles on the basis of the reference signal.

Abstract translation: 要解决的问题：提供基于输入和输出相位的小数部分操作的数字PLL（DPLL）。 解决方案：DPLL累积至少一个输入信号以获得输入相位。 DPLL基于来自振荡器的振荡器信号与参考信号之间的相位差，例如使用时间 - 数字转换器（TDC）来确定输出相位的小数部分。 DPLL根据输入相位的小数部分和输出相位的小数部分来确定相位误差。 DPLL然后根据相位误差产生振荡器的控制信号。 在另一方面，包括合成的累加器的DPLL通过基于参考信号来跟踪振荡器信号周期的数量来确定粗略的输出相位。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2013123237A

公开(公告)日：2013-06-20

申请号：JP2013002736

申请日：2013-01-10

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： SUN BO ,  ANIRUDDHAN SANKARAN

IPC: H03F1/02

CPC classification number: H03F3/3022 ,  H03F1/0272 ,  H03F1/301 ,  H03F1/308 ,  H03F1/3217 ,  H03F3/19 ,  H03F3/245 ,  H03F2200/102 ,  H03F2200/435 ,  H03F2200/451 ,  H03F2200/78 ,  H03F2200/99 ,  H03F2203/30015 ,  H03F2203/30027 ,  H03F2203/30061 ,  H03F2203/30147 ,  H03F2203/30153 ,  H03G1/007 ,  H03G3/3042

Abstract: PROBLEM TO BE SOLVED: To provide techniques for dynamically biasing an amplifier to extend an operating range of the amplifier while conserving power.SOLUTION: A detector is provided to measure output of the amplifier to determine the operating range of the amplifier. Output of the detector is input to a bias adjuster, which outputs a dynamic voltage level supplied to at least one bias transistor in the amplifier. Multiple embodiments of the detector and bias adjuster are disclosed.

Abstract translation: 要解决的问题：提供用于动态地偏置放大器以延长放大器的工作范围同时节省功率的技术。 解决方案：提供检测器来测量放大器的输出以确定放大器的工作范围。 检测器的输出被输入到偏置调节器，该偏置调节器输出提供给放大器中的至少一个偏置晶体管的动态电压电平。 公开了检测器和偏置调节器的多个实施例。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012100295A

公开(公告)日：2012-05-24

申请号：JP2011270475

申请日：2011-12-09

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： ANIRUDDHAN SANKARAN ,  SUN BO ,  JAYARAMAN ARUN ,  GURKANWAL SINGH SAHOTA

IPC: H03D7/00 ,  H04B1/04

CPC classification number: H03D7/165 ,  H04B1/0483 ,  H04B2001/0416 ,  H04B2001/0491

Abstract: PROBLEM TO BE SOLVED: To reduce local oscillator leakage when reducing output power.SOLUTION: A circuit receives a first signal and mixes it with a local oscillator (LO) signal, and outputs a second signal (for example, an RFOUT signal). The circuit includes multiple identical Mixer and Frequency Divider Pair (MFDP) circuits. Each MFDP can be enabled separately. Each MFDP includes a mixer and a frequency divider that provides the mixer with a local version of the LO signal. The MFDP outputs are coupled together so that the output power of the second signal (RFOUT) is the combined output powers of the various MFDPs. By controlling the number of enabled MFDPs, the output power of the second signal is controlled. Because the MFDPs all have identical layouts, accuracy of output power step size is improved. LO signal power within the circuit automatically changes in proportion to the number of enabled MFDPs.

Abstract translation: 要解决的问题：减少输出功率时减少本地振荡器泄漏。 解决方案：电路接收第一个信号并将其与本地振荡器（LO）信号混合，并输出第二个信号（例如，RFOUT信号）。 该电路包括多个相同的混频器和分频器对（MFDP）电路。 每个MFDP可以单独启用。 每个MFDP包括混频器和分频器，为混频器提供本地版本的LO信号。 MFDP输出耦合在一起，使得第二信号（RFOUT）的输出功率是各种MFDP的组合输出功率。 通过控制使能的MFDP的数量，控制第二信号的输出功率。 由于MFDP都具有相同的布局，因此输出功率步长的精度提高。 电路内的LO信号功率自动与启用MFDP的数量成比例。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：SG11202009219QA

公开(公告)日：2020-11-27

申请号：SG11202009219Q

申请日：2019-03-18

Applicant: QUALCOMM INC

Inventor： SUN BO ,  TANG YI ,  BUTTERFIELD DANIEL

IPC: H03K3/011 ,  H03K5/131

Abstract: Aspects generally relate to reducing delay, or phase jitter, in high speed signals transmission. Variations in power supply to ground potential changes the amount of delay introduced by transmit circuitry into the signal being transmitted, resulting in jitter, or phase noise, in the transmitted signal. To reduce phase jitter, or phase noise, aspects disclosed include a variable impedance circuit coupled to the signal distribution network, the impedance level of the variable impedance circuit is adjusted in response to variation in the supply to ground potential, such that the delay introduced by the impedance compensates for changes in the delay due to variations in supply to ground potential, resulting in substantially constant delay.

公开(公告)号：BRPI0406900A

公开(公告)日：2005-12-13

申请号：BRPI0406900

申请日：2004-01-21

Applicant: QUALCOMM INC

Inventor： SUN BO

IPC: H03F1/26 ,  H03F1/32 ,  H03F3/68 ,  H03F3/195

Abstract: A feedforward nonlinearity cancellation scheme is used to improve the linearity of a low noise amplifier (LNA). An LNA incorporates a main amplifier and an auxiliary amplifier couple to receive the same input. The outputs of the main amplifier and the auxiliary amplifier are also coupled. The auxiliary amplifier may be implemented as a very low power auxiliary amplifier having a very low linearity. The output of the auxiliary amplifier contains third-order intermodulation (IM3) products that are of similar amplitude, but opposite phase, to the IM3 products generated by the main amplifier. With the outputs of the main amplifier and the auxiliary amplifier coupled, their respective IM3 products are summed together and effectively cancel each other out. As a result, the output of the LNA contains substantially no IM3 products, and the linearity of the LNA is substantially improved.

公开(公告)号：WO2011084527A2

公开(公告)日：2011-07-14

申请号：PCT/US2010060585

申请日：2010-12-15

Applicant: QUALCOMM INC ,  BALLANTYNE GARY JOHN ,  GENG JIFENG ,  SUN BO

Inventor： BALLANTYNE GARY JOHN ,  GENG JIFENG ,  SUN BO

IPC: H03B19/00 ,  G06F1/08 ,  H03D7/16

CPC classification number: H03B19/00 ,  H03D7/165 ,  H03L7/16

Abstract: Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.

Abstract translation: 抽取第一周期信号以产生第二周期信号的技术。 在示例性实施例中，第一周期信号由可配置的整数比除法器除以且分频器的输出被延迟可配置的分数延迟。 使用例如Σ-Δ调制技术，可配置分数延迟可以是噪声形状，以在宽带宽上扩展分数延迟的量化噪声。 在示例性实施例中，第一和第二周期信号可以用于从单个锁相环（PLL）输出生成通信收发器的发射（TX）和接收（RX）本地振荡器（LO）信号。

公开(公告)号：WO2004068700A3

公开(公告)日：2004-11-04

申请号：PCT/US2004001642

申请日：2004-01-21

Applicant: QUALCOMM INC ,  SUN BO

Inventor： SUN BO

IPC: H03F1/26 ,  H03F1/32 ,  H03F3/68 ,  H03F3/195

CPC classification number: H03F1/26 ,  H03F1/32 ,  H03F1/3223 ,  H03F3/68 ,  H03F2200/294 ,  H03F2200/372

Abstract: A feedforward nonlinearity cancellation scheme is used to improve the linearity of a low noise amplifier (LNA). An LNA incorporates a main amplifier and an auxiliary amplifier couple to receive the same input. The outputs of the main amplifier and the auxiliary amplifier are also coupled. The auxiliary amplifier may be implemented as a very low power auxiliary amplifier having a very low linearity. The output of the auxiliary amplifier contains third-order intermodulation (IM3) products that are of similar amplitude, but opposite phase, to the IM3 products generated by the main amplifier. With the outputs of the main amplifier and the auxiliary amplifier coupled, their respective IM3 products are summed together and effectively cancel each other out. As a result, the output of the LNA contains substantially no IM3 products, and the linearity of the LNA is substantially improved.

公开(公告)号：WO2011028614A3

公开(公告)日：2011-06-30

申请号：PCT/US2010046827

申请日：2010-08-26

Applicant: QUALCOMM INC ,  SUN BO ,  SEGORIA ANTHONY F

Inventor： SUN BO ,  SEGORIA ANTHONY F

IPC: H03F1/30 ,  H03F3/191 ,  H03F3/45

CPC classification number: H03F1/301 ,  H03F1/0283 ,  H03F3/191 ,  H03F3/45183 ,  H03F2203/45544 ,  H03F2203/45562 ,  H03F2203/45652 ,  H04B2001/6908

Abstract: An apparatus including cascaded amplification stages adapted to be biased by a common DC current to generate an amplified output signal from an input signal. A first amplification stage includes a routing network to substantially double an input voltage signal, and a first transconductance gain stage to generate a first current signal from the input voltage signal. A second amplification stage includes a resonator to convert the first current signal into a second voltage signal, and a second transconductance gain stage to generate a second current signal from the first current signal. A third amplification stage includes a current gain stage to generate a third current signal from the second current signal, and a load through which the third current signal flows to generate the output signal.

Abstract translation: 一种设备，包括级联放大级，适于被公共DC电流偏置以从输入信号生成放大的输出信号。 第一放大级包括用于使输入电压信号基本上加倍的路由网络，以及用于从输入电压信号生成第一电流信号的第一跨导增益级。 第二放大级包括用于将第一电流信号转换成第二电压信号的谐振器和用于从第一电流信号生成第二电流信号的第二跨导增益级。 第三放大级包括用于从第二电流信号产生第三电流信号的电流增益级，以及第三电流信号流过的负载以产生输出信号。

公开(公告)号：WO2010105031A3

公开(公告)日：2011-05-05

申请号：PCT/US2010026941

申请日：2010-03-11

Applicant: QUALCOMM INC ,  SUN BO

Inventor： SUN BO

IPC: H04L7/08 ,  H04L27/36

CPC classification number: H04L27/2032 ,  H03C3/00 ,  H03L7/0812 ,  H04L27/205 ,  H04L27/361

Abstract: An apparatus for phase modulation includes a delay locked loop configured to generate from a reference signal a plurality of phase shifted signals, each of the phase shifted signals being locked to the reference signal and having a different phase shift from the other phase shifted signals with respect to the reference signal, and a multiplexer configured to select one of the phase shifted signals.

Abstract translation: 一种用于相位调制的装置包括：延迟锁定环路，被配置为从参考信号产生多个相移信号，每个相移信号被锁定到参考信号，并且与其它相移信号具有不同的相移 以及被配置为选择所述相移信号之一的多路复用器。