公开(公告)号：ES2391714T3

公开(公告)日：2012-11-29

申请号：ES09790669

申请日：2009-07-21

Applicant: QUALCOMM INC

Inventor： GARUDADRI HARINATH ,  MAJUMDAR SOMDEB ,  BUTTERFIELD DANIEL KEYES ,  TANG YI ,  MARTHANDA SANJAY

IPC: H03F3/217

Abstract: Un aparato, que comprende:un medio (106, 200) para cuantificar una señal, en el que el medio para cuantificar la señal consta de tresniveles; yun medio (108, 302) para excitar una carga (110) que tiene bornes primero y segundo, en el que el mediopara excitar la carga está configurado para conmutar los bornes primero y segundo entre carriles de alimentaciónprimero y segundo solamente si la salida del cuantificador se encuentra en uno de los tres niveles, yen el que el medio para excitar una carga está configurado, además, para conmutar los bornes primero ysegundo entre los carriles de alimentación primero y segundo con un ciclo de trabajo ajustable.

公开(公告)号：SG11202009219QA

公开(公告)日：2020-11-27

申请号：SG11202009219Q

申请日：2019-03-18

Applicant: QUALCOMM INC

Inventor： SUN BO ,  TANG YI ,  BUTTERFIELD DANIEL

IPC: H03K3/011 ,  H03K5/131

Abstract: Aspects generally relate to reducing delay, or phase jitter, in high speed signals transmission. Variations in power supply to ground potential changes the amount of delay introduced by transmit circuitry into the signal being transmitted, resulting in jitter, or phase noise, in the transmitted signal. To reduce phase jitter, or phase noise, aspects disclosed include a variable impedance circuit coupled to the signal distribution network, the impedance level of the variable impedance circuit is adjusted in response to variation in the supply to ground potential, such that the delay introduced by the impedance compensates for changes in the delay due to variations in supply to ground potential, resulting in substantially constant delay.

公开(公告)号：WO2014150707A3

公开(公告)日：2015-07-23

申请号：PCT/US2014024035

申请日：2014-03-12

Applicant: QUALCOMM INC

Inventor： TANG YI ,  SUN BO

IPC: G04F10/00 ,  H03L7/08

CPC classification number: H03M1/50 ,  G04F10/005 ,  H03L7/08 ,  H03L7/0991 ,  H03L2207/50

Abstract: A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.

Abstract translation: 时间 - 数字转换器将参考时钟信号和振荡信号的转换时间之间的差异转换成数值信号，其数值信号与转换时序差成比例。 该时间 - 数字转换器包括边缘检测器，时间 - 电压转换器和模 - 数转换器。 边缘检测器适于在参考时钟信号的每个周期期间检测最靠近参考时钟信号的边缘的振荡信号的边沿（跃迁）。 时间 - 电压转换器适于产生与所检测的振荡信号的边沿与基准时钟信号的边沿之间的时间差成比例的模拟信号。 模拟 - 数字转换器适于将模拟信号转换成数字信号，该数字信号的值与振荡信号的检测到的边沿的出现与参考时钟信号的边沿之间的差成比例。