公开(公告)号：AU5968001A

公开(公告)日：2001-11-20

申请号：AU5968001

申请日：2001-05-08

Applicant: QUALCOMM INC

Inventor： PATRICK CHRISTOPHER ,  YOUNIS SAED G

IPC: H03L7/06 ,  H03J7/04 ,  H04B1/16 ,  H03J7/00

Abstract: The frequency error of an oscillator is minimized by characterizing the operating environment of the oscillator. An electronic device monitors parameters that are determined to have an effect on the frequency accuracy of the internal frequency source. Temperature is one parameter known to have an effect on the frequency of the internal frequency source and a primary contributor to device temperature is the RF Power Amplifier (PA). The electronic device collects and stores the activity level of the PA. The effective PA duty cycle over a predetermined period of time is calculated. The LO operating environment is stabilized by operating the PA at the calculated duty cycle when the LO is required to operate in a high stability mode.

公开(公告)号：CA2408595A1

公开(公告)日：2001-11-15

申请号：CA2408595

申请日：2001-05-08

Applicant: QUALCOMM INC

Inventor： YOUNIS SAED G ,  PATRICK CHRISTOPHER

IPC: H03L7/06 ,  H03J7/04 ,  H04B1/16 ,  H03L1/02

Abstract: The frequency error of an oscillator is minimized by characterizing the operating environment of the oscillator. An electronic device monitors parameters that are determined to have an effect on the frequency accuracy of the internal frequency source. Temperature is one parameter known to have an effect on the frequency of the internal frequency source and a primary contributor to device temperature is the RF Power Amplifier (PA). The electronic device collects and stores the activity level of the PA. The effective PA duty cycle over a predetermined period of time is calculated. The LO operating environment is stabilized by operating the PA at the calculated duty cycle when the LO is required to operate in a high stability mode.

公开(公告)号：ZA991677B

公开(公告)日：2000-10-05

申请号：ZA991677

申请日：1999-03-02

Applicant: QUALCOMM INC

Inventor： CICCARELI STEVEN C ,  YOUNIS SAED G

IPC: H04B1/06 ,  H03D20060101 ,  H03K20060101 ,  H04B20060101 ,  H04L20060101 ,  H04B ,  H03D ,  H03K ,  H04L

公开(公告)号：ZA9901677B

公开(公告)日：2000-10-05

申请号：ZA9901677

申请日：1999-03-02

Applicant: QUALCOMM INC

Inventor： CICCARELI STEVEN C ,  YOUNIS SAED G

IPC: H04B1/06 ,  H03D20060101 ,  H03K20060101 ,  H04B20060101 ,  H04L20060101 ,  H04B ,  H03D ,  H03K ,  H04L

公开(公告)号：NO20002931A

公开(公告)日：2000-07-31

申请号：NO20002931

申请日：2000-06-08

Applicant: QUALCOMM INC

Inventor： CICCARELLI STEVEN C ,  YOUNIS SAED G ,  KAUFMAN RALPH E

IPC: H03F1/02 ,  H03F1/34 ,  H03G1/00 ,  H03G3/18 ,  H03G3/20 ,  H04B1/10 ,  H04B1/16

CPC classification number: H03G3/3068 ,  H03F1/0261 ,  H03F1/342 ,  H03F2200/294 ,  H03F2200/331 ,  H03F2200/372 ,  H03G1/0088 ,  H04B1/1027 ,  H04B1/109

公开(公告)号：CA2321582A1

公开(公告)日：1999-09-10

申请号：CA2321582

申请日：1999-03-02

Applicant: QUALCOMM INC

Inventor： YOUNIS SAED G ,  CICCARELLI STEVEN C

IPC: G01S19/07 ,  G01S19/11 ,  G01S19/12 ,  G01S19/31 ,  H04B1/26 ,  H04B1/38 ,  H04B1/40 ,  H04B1/62 ,  H04L27/22

Abstract: A receiver (2) that downconverts input signals modulated using first, second, third and fourth modulation formats to a common intermediate frequency range. The first and second modulation formats are transmitted to the receiver in a first frequency range, the third modulation format is transmitted to the receiver in a second frequency range, and the fourth modulation format is transmitted to the recdeiver in a third frequency range. The input signals are provided to first, second and third band selection filters (10, 12, 14) that respectively select first, second and third frequency ranges. A first downconverter (20) is coupled to an output of the first band selection filter, and downconverts signals from the first frequency range to the common intermediate frequency range. A second downconverter (24) is selectively coupled by a switch (16) to either an output of the second band selection filter (12) or an output of the third band selection filter (14), and downconverts signals from either the second frequency range or the third frequency range to the common intermediate frequency range. The second downconverter has an input coupled to a frequency doubling circuit (26). Switching circuitry (28) selectively couples one of either a first oscillating signal (30) from a voltage controlled oscillator (VCO) (34) having a VCO frequency range or a second oscillating signal (32) at a second frequency that is outside the VCO frequency range to an input of the first downconverter (20) and an input of the frequency doubling circuit (26).

公开(公告)号：AU9308898A

公开(公告)日：1999-04-05

申请号：AU9308898

申请日：1998-09-08

Applicant: QUALCOMM INC

Inventor： BAZARJANI SEYFOLLAH S ,  YOUNIS SAED G

IPC: H03M3/02

Abstract: A bandpass SIGMA DELTA DC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, or a two-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a SIGMA DELTA ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 SIGMA DELTA ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass SIGMA DELTA ADC can also be used in conjunction with undersampling to provide a frequency downconversion.

公开(公告)号：CA2313139C

公开(公告)日：2009-12-15

申请号：CA2313139

申请日：1998-12-08

Applicant: QUALCOMM INC

Inventor： YOUNIS SAED G ,  BUTTERFIELD DANIEL K ,  BAZARJANI SEYFOLLAH S ,  CICCARELLI STEVEN C

IPC: H03M1/66 ,  H04B1/16 ,  H03D3/00 ,  H03D7/16 ,  H03M1/12 ,  H03M3/02 ,  H04B1/26

Abstract: A receiver comprising a sigma-delta analog-to-digital converter (.SIGMA..DELTA. ADC) can be utilized in one of four configurations, as a subsampling bandpass receiver, a subsampling baseband receiver, a Nyquist sampling bandpass receiver, or a Nyquist sampling baseband receiver. For subsampling .SIGMA..DELTA. receivers, the sampling frequency i s less than twice the center frequency of the input signal into the .SIGMA..DELTA. ADC. For Nyquist sampling .SIGMA..DELTA. receivers, the sampling frequency i s at least twice the highest frequency of the input signal into the .SIGMA..DELTA. ADC. For baseband .SIGMA..DELTA. receivers, the center frequency of the outp ut signal from the .SIGMA..DELTA. ADC is approximately zero or DC. For bandpass .SIGMA..DELTA. receivers, the center frequency of the output signal from the .SIGMA..DELTA. ADC is greater than zero. The sampling frequency can be selected based on the bandwidth of the input signal to simplify the design of the digital circuits used to process the output samples from the .SIGMA..DELTA. ADC. Furthermore, the center frequency of the input signal can be selected based on the sampling frequency and the bandwidth of the input signal. The .SIGMA..DELTA. ADC within the receiver provides many benefits.

公开(公告)号：CA2321582C

公开(公告)日：2009-11-17

申请号：CA2321582

申请日：1999-03-02

Applicant: QUALCOMM INC

Inventor： CICCARELLI STEVEN C ,  YOUNIS SAED G

IPC: H04B1/40 ,  G01S19/07 ,  G01S19/11 ,  G01S19/12 ,  G01S19/31 ,  H04B1/26 ,  H04B1/38 ,  H04B1/62 ,  H04L27/22

Abstract: A receiver (2) that down-converts input signals modu-lated using first, second, third and fourth modulation formats to a common intermediate fre-quency range. The first and second modulation formats are transmitted to the receiver in a first frequency range, the third modulation format is transmit-ted to the receiver in a second frequency range, and the fourth modulation format is transmit-ted to the recdeiver in a third frequency range. The input sig-nals are provided to first, sec-ond and third band selection fil-ters (10, 12, 14) that respec-tively select first, second and third frequency ranges. A first downconverter (20) is coupled to an output of the first band se-lection filter, and downconverts signals from the first frequency range to the common intermediate frequency range. A second downconverter (24) is selectively coupled by a switch (16) to either an output of the second band selection filter (12) o r an output of the third band selection filter (14), and downconverts signals from either the second frequency range or the third frequency range to the common intermediate frequency range. The second downconverter has an input coupled to a frequency doubling circuit (26). Switching circuitry (28) selectively couples one of either a first oscillating signal (30) from avoltage controlled oscillator (VCO) (34) havin g a VCO frequency range or a second oscillating signal (32) at a second frequency that is outside the VCO frequency range to an input of the first downconverter (20) and an input of the frequency doubling circuit (26).

公开(公告)号：AU2006203601B2

公开(公告)日：2009-11-12

申请号：AU2006203601

申请日：2006-08-21

Applicant: QUALCOMM INC

Inventor： ZHANG HAITAO ,  SIMIC EMILIJA ,  LIN JIAN ,  FILIPOVIC DANIEL ,  WILBORN THOMAS ,  KAUFMAN RALPH ,  YOUNIS SAED G

IPC: H03G3/30 ,  H04B1/04 ,  H03G3/20 ,  H04B7/005 ,  H04B7/24

Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.