公开(公告)号：WO2012151331A1

公开(公告)日：2012-11-08

申请号：PCT/US2012/036196

申请日：2012-05-02

Applicant: QUALCOMM Incorporated ,  PLONDKE, Erich James ,  CODRESCU, Lucian ,  TABONY, Charles Joseph ,  VENKUMAHANTI, Suresh K. ,  INGLE, Ajay Anant

Inventor： PLONDKE, Erich James ,  CODRESCU, Lucian ,  TABONY, Charles Joseph ,  VENKUMAHANTI, Suresh K. ,  INGLE, Ajay Anant

IPC: G06F9/30

CPC classification number: G06F9/30192 ,  G06F9/30167

Abstract: Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.

Abstract translation: 程序通常需要不能以本机指令格式编码的常量，例如32位。 为了提供扩展常数，形成具有恒定扩展器信息和目标指令的指令包。 编码为恒定扩展器指令的恒定扩展器信息提供第一组常量位，例如26位，目标指令提供第二组常数位，例如6位。 第一组常数位与第二组常数位组合以产生用于执行目标指令的扩展常数。 扩展常数可以用作扩展源操作数，存储器访问指令的扩展地址，分支类型的指令的扩展地址等。 多个恒定扩展器指令可以一起使用以提供比单个扩展指令可以提供的更大的常数。

公开(公告)号：WO2012006277A1

公开(公告)日：2012-01-12

申请号：PCT/US2011/042942

申请日：2011-07-05

Applicant: QUALCOMM INCORPORATED ,  INGLE, Ajay Anant ,  PLONDKE, Erich James ,  RAB, Muhammad T.

Inventor： INGLE, Ajay Anant ,  PLONDKE, Erich James ,  RAB, Muhammad T.

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/681 ,  G06F2212/682 ,  Y02D10/13

Abstract: A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory instruction, setting a first field associated with an entry of the first TLB to indicate use of the entry. The method also includes setting a second field to indicate that the entry in the first TLB matches a corresponding entry in a second TLB.

Abstract translation: 公开了一种用于管理翻译后备缓冲器（TLB）的系统和方法。 在特定实施例中，管理第一TLB的方法包括响应于存储器指令的开始执行，设置与第一TLB的条目相关联的第一字段以指示条目的使用。 该方法还包括设置第二字段以指示第一TLB中的条目与第二TLB中的对应条目匹配。

公开(公告)号：WO2010144832A1

公开(公告)日：2010-12-16

申请号：PCT/US2010/038355

申请日：2010-06-11

Applicant: QUALCOMM Incorporated ,  PLONDKE, Erich James ,  CODRESCU, Lucian ,  INGLE, Ajay Anant

Inventor： PLONDKE, Erich James ,  CODRESCU, Lucian ,  INGLE, Ajay Anant

IPC: G06F12/10 ,  G06F12/12

CPC classification number: G06F12/121 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/127

Abstract: In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cache having at least two partitions. The circuit device also includes a control logic circuit adapted to identify a partition replacement policy associated with the identified one of the at least two partitions based on a partition indicator. The control logic circuit controls replacement of data within the cache according to the identified partition replacement policy in response to a cache miss event.

Abstract translation: 在特定实施例中，电路设备包括被配置为接收虚拟地址并将虚拟地址转换为具有至少两个分区的高速缓存的物理地址的翻译后备缓冲器（TLB）。 电路装置还包括控制逻辑电路，其适于基于分区指示符来识别与所识别的至少两个分区中的一个分区相关联的分区替换策略。 控制逻辑电路响应于高速缓存未命中事件，根据所识别的分区替换策略来控制高速缓存内的数据的替换。

公开(公告)号：WO2008055099A2

公开(公告)日：2008-05-08

申请号：PCT/US2007/082824

申请日：2007-10-29

Applicant: QUALCOMM Incorporated ,  LIN, Jentsung ,  INGLE, Ajay Anant

Inventor： LIN, Jentsung ,  INGLE, Ajay Anant

CPC classification number: G11C29/26 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C8/12 ,  G11C29/1201 ,  G11C29/38

Abstract: In a particular embodiment, a method is disclosed that includes receiving a first sense output and a second sense output of a sense amplifier at a first tri-state device coupled to a first bus, receiving the first sense output and the second sense output of the sense amplifier at a second tri-state device coupled to a second bus, and selectively activating one of the first tri-state device and the second tri-state device to drive the first bus or the second bus in response to a bus selection input.

Abstract translation: 在一个具体实施例中，公开了一种方法，其包括在耦合到第一总线的第一三态设备处接收读出放大器的第一感测输出和第二感测输出，接收第一感测输出和第二感测输出 耦合到第二总线的第二三态装置处的读出放大器，以及响应于总线选择输入而选择性地激活第一三态装置和第二三态装置之一以驱动第一总线或第二总线。

公开(公告)号：EP2974051B1

公开(公告)日：2019-05-08

申请号：EP14717009.6

申请日：2014-03-12

Applicant: Qualcomm Incorporated

Inventor： MATHEW, Deepak ,  INGLE, Ajay Anant ,  ZENG,Mao ,  HOFFMAN, Marc M.

IPC: H04B1/7093 ,  H04B1/7075 ,  H03H17/02 ,  H04L25/02

公开(公告)号：EP3026549A3

公开(公告)日：2016-06-15

申请号：EP15190667.4

申请日：2012-08-24

Applicant: Qualcomm Incorporated

Inventor： FRIDMAN, Jose ,  INGLE, Ajay Anant ,  MATHEW, Deepak ,  HOFFMAN, Marc, M. ,  LOPEZ, Michael, John

IPC: G06F9/30 ,  G06F15/80

CPC classification number: G06F15/8084 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109

Abstract: Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.

Abstract translation: 公开了一种矢量处理器中的数据提取系统和方法。 在特定实施例中，矢量处理器中的数据提取方法包括将至少一个数据元素复制到置换网络的源寄存器。 该方法包括重新排序源寄存器的多个数据元素，用重新排序的数据元素填充置换网络的目的地寄存器，并且将重新排序的数据元素从目的地寄存器复制到存储器。

公开(公告)号：EP2082399A2

公开(公告)日：2009-07-29

申请号：EP07863608.1

申请日：2007-10-29

Applicant: QUALCOMM Incorporated

Inventor： LIN, Jentsung ,  INGLE, Ajay Anant

IPC: G11C7/10 ,  G11C11/417 ,  G11C29/02

CPC classification number: G11C29/26 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C8/12 ,  G11C29/1201 ,  G11C29/38

Abstract: In a particular embodiment, a method is disclosed that includes receiving a first sense output and a second sense output of a sense amplifier at a first tri-state device coupled to a first bus, receiving the first sense output and the second sense output of the sense amplifier at a second tri-state device coupled to a second bus, and selectively activating one of the first tri-state device and the second tri-state device to drive the first bus or the second bus in response to a bus selection input.

公开(公告)号：WO2018022191A3

公开(公告)日：2018-02-01

申请号：PCT/US2017/035803

申请日：2017-06-02

Applicant: QUALCOMM INCORPORATED

Inventor： MATHEW, Deepak ,  INGLE, Ajay Anant ,  SUN, Yurong ,  ZHU, Jianming ,  HOFFMAN, Marc

IPC: G06F17/17 ,  G06F7/544 ,  G06F9/30

Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.

公开(公告)号：WO2017014892A1

公开(公告)日：2017-01-26

申请号：PCT/US2016/038487

申请日：2016-06-21

Applicant: QUALCOMM INCORPORATED

Inventor： MAHURIN, Eric Wayne ,  INGLE, Ajay Anant

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/30112

Abstract: Systems and methods relate to a mixed-width single instruction multiple data (SIMD) instruction which has at least a source vector operand comprising data elements of a first bit-width and a destination vector operand comprising data elements of a second bit-width, wherein the second bit-width is either half of or twice the first bit-width. Correspondingly, one of the source or destination vector operands is expressed as a pair of registers, a first register and a second register. The other vector operand is expressed as a single register. Data elements of the first register correspond to even-numbered data elements of the other vector operand expressed as a single register, and data elements of the second register correspond to data elements of the other vector operand expressed as a single register.

Abstract translation: 系统和方法涉及混合宽度单指令多数据（SIMD）指令，其具有至少包括第一位宽的数据元素和包含第二位宽的数据元素的目的地向量操作数的源向量操作数，其中 第二个位宽是第一个位宽的一半或两倍。 相应地，源或目标向量操作数之一被表示为一对寄存器，第一寄存器和第二寄存器。 另一个向量操作数表示为单个寄存器。 第一寄存器的数据元素对应于表示为单个寄存器的另一向量操作数的偶数数据元，第二寄存器的数据元对应于表示为单个寄存器的另一向量操作数的数据元。

公开(公告)号：WO2015023465A1

公开(公告)日：2015-02-19

申请号：PCT/US2014/049604

申请日：2014-08-04

Applicant: QUALCOMM INCORPORATED

Inventor： INGLE, Ajay Anant ,  HOFFMAN, Marc Murray ,  MATHEW, Deepak ,  ZENG, Mao

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897

Abstract: In a particular embodiment, a method includes executing a vector instruction at a processor. The vector instruction includes a vector input that includes a plurality of elements. Executing the vector instruction includes providing a first element of the plurality of elements as a first output. Executing the vector instruction further includes performing an arithmetic operation on the first element and a second element of the plurality of elements to provide a second output. Executing the vector instruction further includes storing the first output and the second output in an output vector.

Abstract translation: 在特定实施例中，一种方法包括在处理器处执行向量指令。 矢量指令包括包括多个元素的矢量输入。 执行向量指令包括提供多个元素中的第一元素作为第一输出。 执行向量指令还包括对第一元素和多个元素的第二元素执行算术运算以提供第二输出。 执行向量指令还包括将第一输出和第二输出存储在输出向量中。