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    INSTRUCTION APPLICABLE TO RADIX-3 BUTTERFLY COMPUTATION
    1.
    发明申请
    INSTRUCTION APPLICABLE TO RADIX-3 BUTTERFLY COMPUTATION 审中-公开

    公开(公告)号：WO2023049592A1

    公开(公告)日：2023-03-30

    申请号：PCT/US2022/075405

    申请日：2022-08-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： LAHOTI, Saurabh ,  HOFFMAN, Marc ,  SUDARSANAN, Srijesh ,  DONG, Hongfeng

    IPC: G06F17/14 ,  G06F9/00

    Abstract: A device includes a processor and a memory configured to store instructions. The processor is configured to receive a particular instruction from among the instructions and to execute the particular instruction to generate first output data corresponding to a sum of first input data and second input data. The processor is also configured to execute the particular instruction to perform a divide operation on the second input data and to generate second output data corresponding to a difference of the first input data and a result of the divide operation.

    SYSTEM AND METHOD FOR PIECEWISE LINEAR APPROXIMATION
    2.
    发明申请
    SYSTEM AND METHOD FOR PIECEWISE LINEAR APPROXIMATION 审中-公开
    分块线性近似的系统和方法

    公开(公告)号：WO2018022191A2

    公开(公告)日：2018-02-01

    申请号：PCT/US2017/035803

    申请日：2017-06-02

    Applicant: QUALCOMM INCORPORATED

    Inventor： MATHEW, Deepak ,  INGLE, Ajay Anant ,  SUN, Yurong ,  ZHU, Jianming ,  HOFFMAN, Marc

    IPC: G06F17/17

    Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.

    Abstract translation: 一种装置包括被配置为存储输入值的向量的一个或多个寄存器。 该装置还包括系数确定单元，被配置为响应于单个指令的处理器的执行，选择多个分段分析系数。 多个分段分析系数包括一组或多组分段分析系数，并且每组分段分析系数对应于输入值的向量的输入值。 该装置进一步包括算术逻辑电路，该算术逻辑电路被配置为响应于至少单个指令的执行，基于多个分段分析系数和输入值向量来确定函数的估计输出值。

    PERMUTATION INSTRUCTION
    3.
    发明申请
    PERMUTATION INSTRUCTION 审中-公开

    公开(公告)号：WO2023049593A1

    公开(公告)日：2023-03-30

    申请号：PCT/US2022/075406

    申请日：2022-08-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： SUDARSANAN, Srijesh ,  MATHEW, Deepak ,  HOFFMAN, Marc ,  SWEENEY, Gerald ,  BALASUBRAMANIAN, Sundar Rajan ,  DONG, Hongfeng ,  SUN, Yurong ,  SADEGHZADEH, Seyedmehdi

    IPC: G06F9/30

    Abstract: A device includes a vector register file, a memory, and a processor. The vector register file includes a plurality of vector registers. The memory is configured to store a permutation instruction. The processor is configured to access a periodicity parameter of the permutation instruction. The periodicity parameter indicates a count of a plurality of data sources that contain source data for the permutation instruction. The processor is also configured to execute the permutation instruction to, for each particular element of multiple elements of a first permutation result register of the plurality of vector registers, select a data source of the plurality of data sources based at least in part on the count of the plurality of data sources and populate the particular element based on a value in a corresponding element of the selected data source.

    FAST FOURIER TRANSFORM USING PHASOR TABLE
    4.
    发明申请
    FAST FOURIER TRANSFORM USING PHASOR TABLE 审中-公开

    公开(公告)号：WO2023049594A1

    公开(公告)日：2023-03-30

    申请号：PCT/US2022/075410

    申请日：2022-08-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： SRINIVASAN, Santosh Srivatsan ,  HOFFMAN, Marc ,  SUDARSANAN, Srijesh ,  MATHEW, Deepak ,  DONG, Hongfeng ,  SWEENEY, Gerald

    IPC: G06F17/14 ,  G06F9/00

    Abstract: A device includes a memory configured to store a fast Fourier transform (FFT) instruction and parameters of the FFT instruction, a read-only memory including a phasor table, and a processor. The processor is configured to execute the FFT instruction to determine, based on the parameters of the FFT instruction, a start value and a step size. The processor is configured to execute the FFT instruction to access the phasor table according to the start value and the step size to obtain a set of twiddle values. The processor is also configured to execute the FFT instruction to compute, for each pair of input values in a set of input data, an output value based on the pair of input values and a twiddle value, of the set of twiddle values, that corresponds to that pair of input values.

    SYSTEM AND METHOD FOR PIECEWISE LINEAR APPROXIMATION
    5.
    发明申请
    SYSTEM AND METHOD FOR PIECEWISE LINEAR APPROXIMATION 审中-公开

    公开(公告)号：WO2018022191A3

    公开(公告)日：2018-02-01

    申请号：PCT/US2017/035803

    申请日：2017-06-02

    Applicant: QUALCOMM INCORPORATED

    Inventor： MATHEW, Deepak ,  INGLE, Ajay Anant ,  SUN, Yurong ,  ZHU, Jianming ,  HOFFMAN, Marc

    IPC: G06F17/17 ,  G06F7/544 ,  G06F9/30

    Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.

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