公开(公告)号：WO2018022191A2

公开(公告)日：2018-02-01

申请号：PCT/US2017/035803

申请日：2017-06-02

Applicant: QUALCOMM INCORPORATED

Inventor： MATHEW, Deepak ,  INGLE, Ajay Anant ,  SUN, Yurong ,  ZHU, Jianming ,  HOFFMAN, Marc

IPC: G06F17/17

Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.

Abstract translation: 一种装置包括被配置为存储输入值的向量的一个或多个寄存器。 该装置还包括系数确定单元，被配置为响应于单个指令的处理器的执行，选择多个分段分析系数。 多个分段分析系数包括一组或多组分段分析系数，并且每组分段分析系数对应于输入值的向量的输入值。 该装置进一步包括算术逻辑电路，该算术逻辑电路被配置为响应于至少单个指令的执行，基于多个分段分析系数和输入值向量来确定函数的估计输出值。

公开(公告)号：WO2014062445A1

公开(公告)日：2014-04-24

申请号：PCT/US2013/064063

申请日：2013-10-09

Applicant: QUALCOMM INCORPORATED

Inventor： INGLE, Ajay Anant ,  HOFFMAN, Marc M. ,  MATHEW, Deepak

IPC: G06F9/30

CPC classification number: G06F9/30141 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3012

Abstract: A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.

Abstract translation: 一种方法包括根据选择模式将多个地址线的第一地址线和多个地址线的第二地址线选择性地耦合到向量寄存器堆的多个元素组的第一元素组。 该方法还包括通过单个读取端口访问由第一地址线选择性寻址的存储在第一元素库内的数据。

公开(公告)号：WO2014042819A1

公开(公告)日：2014-03-20

申请号：PCT/US2013/055335

申请日：2013-08-16

Applicant: QUALCOMM INCORPORATED

Inventor： MATHEW, Deepak ,  SHIH, Garret Webster ,  FRIDMAN, Jose ,  BROWN, Robin Lee

IPC: H04W52/02

CPC classification number: H04W52/02 ,  H04W52/0245 ,  H04W52/028 ,  H04W52/0287 ,  Y02D70/00 ,  Y02D70/1222 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/146

Abstract: A system and method dynamically scale power consumed by the circuitry of an electronic device based on channel state and/or data rate. The electronic device then operates according to the power scaling. The scaling may be in accordance with an effective data rate, a number of multiple input multiple output (MIMO) layers, receiver type, a cell scenario, or a number of carriers. A number of MIMO layers can be predicted based on at least one of channel conditions or a channel quality index (CQI).

Abstract translation: 系统和方法基于信道状态和/或数据速率来动态地缩放由电子设备的电路消耗的功率。 电子设备然后根据功率缩放来操作。 缩放可以根据有效数据速率，多输入多输出（MIMO）层，接收器类型，单元方案或多个载波来实现。 可以基于信道条件或信道质量指数（CQI）中的至少一个来预测多个MIMO层。

公开(公告)号：WO2014031129A1

公开(公告)日：2014-02-27

申请号：PCT/US2012/052328

申请日：2012-08-24

Applicant: QUALCOMM INCORPORATED ,  FRIDMAN, Jose ,  INGLE, Ajay Anant ,  MATHEW, Deepak ,  HOFFMAN, Marc, M. ,  LOPEZ, Michael, John

Inventor： FRIDMAN, Jose ,  INGLE, Ajay Anant ,  MATHEW, Deepak ,  HOFFMAN, Marc, M. ,  LOPEZ, Michael, John

IPC: G06F9/30 ,  G06F15/80

CPC classification number: G06F15/8084 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109

Abstract: Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.

Abstract translation: 公开了一种向量处理器中数据提取的系统和方法。 在特定实施例中，向量处理器中的数据提取方法包括将至少一个数据元素复制到置换网络的源寄存器。 该方法包括重新排序源寄存器的多个数据元素，用重新排序的数据元素填充置换网络的目的地寄存器，以及将重新排序的数据元素从目的寄存器复制到存储器。

公开(公告)号：WO2023049593A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/075406

申请日：2022-08-24

Applicant: QUALCOMM INCORPORATED

Inventor： SUDARSANAN, Srijesh ,  MATHEW, Deepak ,  HOFFMAN, Marc ,  SWEENEY, Gerald ,  BALASUBRAMANIAN, Sundar Rajan ,  DONG, Hongfeng ,  SUN, Yurong ,  SADEGHZADEH, Seyedmehdi

IPC: G06F9/30

Abstract: A device includes a vector register file, a memory, and a processor. The vector register file includes a plurality of vector registers. The memory is configured to store a permutation instruction. The processor is configured to access a periodicity parameter of the permutation instruction. The periodicity parameter indicates a count of a plurality of data sources that contain source data for the permutation instruction. The processor is also configured to execute the permutation instruction to, for each particular element of multiple elements of a first permutation result register of the plurality of vector registers, select a data source of the plurality of data sources based at least in part on the count of the plurality of data sources and populate the particular element based on a value in a corresponding element of the selected data source.

公开(公告)号：WO2014150733A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/024089

申请日：2014-03-12

Applicant: QUALCOMM INCORPORATED

Inventor： MATHEW, Deepak ,  INGLE, Ajay Anant ,  ZENG, Mao ,  HOFFMAN, Marc M.

IPC: H04B1/7093 ,  H04B1/7075 ,  H03H17/02

CPC classification number: H04L25/0212 ,  H04B1/70752 ,  H04B1/7093 ,  H04B2201/70707

Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

Abstract translation: 一种装置包括选择逻辑，其被配置为选择存储在第一组寄存器中的第一组采样的第一子集。 第一子集包括存储在第一组寄存器的第一寄存器中的第一样本，并且还包括存储在第一组寄存器的第二寄存器上的第二样本。 该装置还包括移位逻辑，配置成移位存储在第二组寄存器中的第二组采样。 该装置还包括信道估计器，其被配置为基于第一子集生成与信道估计相关联的第一值，并且还基于所移位的第二组样本的第二子集。

公开(公告)号：WO2023049594A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/075410

申请日：2022-08-24

Applicant: QUALCOMM INCORPORATED

Inventor： SRINIVASAN, Santosh Srivatsan ,  HOFFMAN, Marc ,  SUDARSANAN, Srijesh ,  MATHEW, Deepak ,  DONG, Hongfeng ,  SWEENEY, Gerald

IPC: G06F17/14 ,  G06F9/00

Abstract: A device includes a memory configured to store a fast Fourier transform (FFT) instruction and parameters of the FFT instruction, a read-only memory including a phasor table, and a processor. The processor is configured to execute the FFT instruction to determine, based on the parameters of the FFT instruction, a start value and a step size. The processor is configured to execute the FFT instruction to access the phasor table according to the start value and the step size to obtain a set of twiddle values. The processor is also configured to execute the FFT instruction to compute, for each pair of input values in a set of input data, an output value based on the pair of input values and a twiddle value, of the set of twiddle values, that corresponds to that pair of input values.

公开(公告)号：WO2018022191A3

公开(公告)日：2018-02-01

申请号：PCT/US2017/035803

申请日：2017-06-02

Applicant: QUALCOMM INCORPORATED

Inventor： MATHEW, Deepak ,  INGLE, Ajay Anant ,  SUN, Yurong ,  ZHU, Jianming ,  HOFFMAN, Marc

IPC: G06F17/17 ,  G06F7/544 ,  G06F9/30

Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.

公开(公告)号：WO2017052833A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/046736

申请日：2016-08-12

Applicant: QUALCOMM INCORPORATED

Inventor： SUBRAHMANYA, Parvathanathan ,  SHEN, Qiang ,  KHANDEKAR, Aamod, Dinkar ,  MOTAMED, Mariam ,  CHEN, Wanshi ,  PAN, Hanfang ,  MATHEW, Deepak

IPC: H04L5/00 ,  H04L1/00 ,  H04W72/12 ,  H04W24/10

CPC classification number: H04W24/10 ,  H04L1/0026 ,  H04L1/0027 ,  H04L1/0029 ,  H04L5/001 ,  H04L5/0048 ,  H04L5/0057 ,  H04W8/22

Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) utilizing enhanced carrier aggregation (eCA) may identify a limit to the number of channel state feedback (CSF) processes it is capable of supporting. The UE may transmit an indication of this limit to a base station, which may configure the UE for channel state reporting, and send channel state reporting triggers according to the indicated limit. The UE's determination of the limit to the number of CSF processes may be based on various transmit or receive antenna configurations. A single trigger may correspond to reports covering multiple subframes and/or component carriers. The base station may also arrange the channel state reporting configuration to reduce the peak number of channel state reports that the UE processes during each subframe. The UE may also determine that a number of channel state processes needed to support channel state reporting in a subframe exceeds its capacity. The UE may then prioritize the channel state processes and/or may transmit one or more non-current reports.

Abstract translation: 描述了用于无线通信的方法，系统和设备。 利用增强的载波聚合（eCA）的用户设备（UE）可以识别其能够支持的信道状态反馈（CSF）过程的数量的限制。 UE可以向基站发送该限制的指示，该基站可以将UE配置为信道状态报告，并根据指示的限制发送信道状态报告触发。 UE对CSF过程数量的限制的确定可以基于各种发射或接收天线配置。 单个触发器可以对应于覆盖多个子帧和/或分量载波的报告。 基站还可以布置信道状态报告配置以减少在每个子帧期间UE处理的信道状态报告的峰值数量。 UE还可以确定在子帧中支持信道状态报告所需的信道状态过程的数量超过其容量。 然后，UE可以优先化信道状态过程和/或可以发送一个或多个非当前报告。

公开(公告)号：WO2015023465A1

公开(公告)日：2015-02-19

申请号：PCT/US2014/049604

申请日：2014-08-04

Applicant: QUALCOMM INCORPORATED

Inventor： INGLE, Ajay Anant ,  HOFFMAN, Marc Murray ,  MATHEW, Deepak ,  ZENG, Mao

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897

Abstract: In a particular embodiment, a method includes executing a vector instruction at a processor. The vector instruction includes a vector input that includes a plurality of elements. Executing the vector instruction includes providing a first element of the plurality of elements as a first output. Executing the vector instruction further includes performing an arithmetic operation on the first element and a second element of the plurality of elements to provide a second output. Executing the vector instruction further includes storing the first output and the second output in an output vector.

Abstract translation: 在特定实施例中，一种方法包括在处理器处执行向量指令。 矢量指令包括包括多个元素的矢量输入。 执行向量指令包括提供多个元素中的第一元素作为第一输出。 执行向量指令还包括对第一元素和多个元素的第二元素执行算术运算以提供第二输出。 执行向量指令还包括将第一输出和第二输出存储在输出向量中。