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    EFFICIENT INTERRUPT RETURN ADDRESS SAVE MECHANISM
    11.
    发明申请
    EFFICIENT INTERRUPT RETURN ADDRESS SAVE MECHANISM 审中-公开
    有效的中断返回地址保存机制

    公开(公告)号：WO2008014287A1

    公开(公告)日：2008-01-31

    申请号：PCT/US2007/074263

    申请日：2007-07-24

    Applicant: QUALCOMM INCORPORATED ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  MCILVAINE, Michael Scott

    Inventor： SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  MCILVAINE, Michael Scott

    IPC: G06F9/32 ,  G06F9/38 ,  G06F9/42 ,  G06F9/46 ,  G06F9/48

    CPC classification number: G06F9/30054 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/3836

    Abstract: A system, apparatus and method for efficiently processing interrupts using general purpose registers in a pipelined processor. In accordance with the present disclosure, a register file may be updated to efficiently save an interrupt return address. When an interrupt request is received by the system's processor, or when the request is issued in the execution of a program, a pseudo-instruction is generated. This pseudo-instruction travels down the pipeline in the same way as other instructions and updates the register file by causing the register file to be written with the return address of the last instruction for which processing has not been completed.

    Abstract translation: 一种用于在流水线处理器中使用通用寄存器来有效地处理中断的系统，装置和方法。 根据本公开，可以更新寄存器文件以有效地保存中断返回地址。 当系统的处理器接收到中断请求时，或者当执行程序发出请求时，产生伪指令。 该伪指令以与其他指令相同的方式沿着流水线行进，并通过使用寄存器文件写入尚未完成处理的最后一条指令的返回地址来更新寄存器文件。

    VIRTUALLY-TAGGED INSTRUCTION CACHE WITH PHYSICALLY-TAGGED BEHAVIOR
    12.
    发明申请
    VIRTUALLY-TAGGED INSTRUCTION CACHE WITH PHYSICALLY-TAGGED BEHAVIOR 审中-公开
    虚拟标记的具有物理标记行为的指令缓存

    公开(公告)号：WO2007124307A2

    公开(公告)日：2007-11-01

    申请号：PCT/US2007/066802

    申请日：2007-04-17

    Applicant: QUALCOMM INCORPORATED ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  STREETT, Daren Eugene

    Inventor： SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  STREETT, Daren Eugene

    CPC classification number: G06F12/1063 ,  G06F12/0891 ,  G06F2212/1056 ,  G06F2212/683

    Abstract: An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.

    Abstract translation: 公开了一种具有虚拟标记的指令高速缓存的指令高速缓存系统，从软件程序角度来看，其操作就好像它是物理标记的指令高速缓存。 指令高速缓存系统还包括用于地址转换的装置，它响应地址转换无效指令和控制逻辑电路。 控制逻辑电路被配置为响应于地址转换无效指令使虚拟标记的指令高速缓存中的条目无效。

    UNALIGNED MEMORY ACCESS PREDICTION
    15.
    发明申请
    UNALIGNED MEMORY ACCESS PREDICTION 审中-公开

    公开(公告)号：WO2006089194A2

    公开(公告)日：2006-08-24

    申请号：PCT/US2006/005782

    申请日：2006-02-16

    Applicant: QUALCOMM INCORPORATED ,  BRIDGES, Jeffrey Todd ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

    Inventor： BRIDGES, Jeffrey Todd ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

    CPC classification number: G06F9/30043 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3832 ,  G06F9/3855

    Abstract: In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The additional micro-operation accesses the memory falling across a predetermined address boundary. Predicting the misalignment and generating a micro-operation early in the pipeline ensures that sufficient pipeline control resources are available to generate and track the additional micro-operation, avoiding a pipeline flush if the resources are not available at the time of effective address generation. The misalignment prediction may employ known conditional branch prediction techniques, such as a flag, a bimodal counter, a local predictor, a global predictor, and combined predictors. A misalignment predictor may be enabled or biased by a memory access instruction flag or misaligned instruction type.

    Abstract translation: 在指令执行流水线中，预测存储器访问指令的未对准。 基于该预测，在存储器访问指令的有效地址生成之前在流水线中生成附加的微操作。 附加的微操作访问落在预定地址边界上的存储器。 预测未对准并在管道早期生成微操作确保足够的流水线控制资源可用于生成和跟踪附加的微操作，如果资源在有效地址生成时不可用，则避免管道冲洗。 不对准预测可以使用已知的条件分支预测技术，例如标志，双模计数器，局部预测器，全局预测器和组合预测器。 未对准预测器可能被存储器访问指令标志或未对准指令类型使能或偏置。

    PRE-DECODE ERROR HANDLING VIA BRANCH CORRECTION
    17.
    发明申请
    PRE-DECODE ERROR HANDLING VIA BRANCH CORRECTION 审中-公开
    通过分支纠正预解码错误处理

    公开(公告)号：WO2006057907A2

    公开(公告)日：2006-06-01

    申请号：PCT/US2005/041850

    申请日：2005-11-18

    Applicant: QUALCOMM Incorporated ,  SMITH, Rodney Wayne ,  STEMPEL, Brian Michael ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

    Inventor： SMITH, Rodney Wayne ,  STEMPEL, Brian Michael ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

    IPC: G06F9/30

    CPC classification number: G06F9/3861 ,  G06F9/30152 ,  G06F9/3017 ,  G06F9/382

    Abstract: In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as "mispredicted not taken" with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.

    Abstract translation: 在流水线处理器中，指令在被存储在高速缓存中之前被预解码，在流水线中执行期间检测到不正确的预解码指令。 相应的指令在高速缓存中失效，并且该指令被强制评估为分支指令。 特别地，分支指令被评估为“未预测到错误预测” 与不正确的预解码指令地址的分支目标地址。 这与无效的高速缓存行一起导致不正确的预解码指令从具有精确地址的存储器重新获取。 重新获取的指令然后被正确地预解码，写入缓存并执行。

    SYSTEMS AND METHODS OF EXECUTING MULTIPLE HYPERVISORS
    19.
    发明申请
    SYSTEMS AND METHODS OF EXECUTING MULTIPLE HYPERVISORS 审中-公开
    多重执行机构的系统与方法

    公开(公告)号：WO2014159405A1

    公开(公告)日：2014-10-02

    申请号：PCT/US2014/023445

    申请日：2014-03-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： PLONDKE, Erich James ,  CODRESCU, Lucian ,  KOOB, Christopher Edward ,  PATEL, Piyush ,  SARTORIUS, Thomas Andrew

    IPC: G06F9/455 ,  G06F9/50 ,  G06F12/10

    CPC classification number: G06F9/45533 ,  G06F9/5016 ,  G06F12/109 ,  G06F2212/1021 ,  G06F2212/151 ,  G06F2212/656

    Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.

    Abstract translation: 一种装置包括可在第一组处理器上执行的主管理程序，以及可在第二组处理器上执行的辅管理程序。 主管理程序可以定义资源的设置，次管理程序可以使用基于主管理程序定义的设置的资源。 例如，主管理程序可以为二级管理程序编程内存地址转换映射。 主管理程序和辅助管理程序可以包括它们自己的调度器。

    METHODS AND SYSTEMS FOR CHECKING RUN-TIME INTEGRITY OF SECURE CODE
    20.
    发明申请
    METHODS AND SYSTEMS FOR CHECKING RUN-TIME INTEGRITY OF SECURE CODE 审中-公开
    用于检查安全代码的运行时完整性的方法和系统

    公开(公告)号：WO2011016793A2

    公开(公告)日：2011-02-10

    申请号：PCT/US2009/050556

    申请日：2009-07-14

    Applicant: QUALCOMM Incorporated ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew ,  MILLENDORF, Steven M.

    Inventor： BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew ,  MILLENDORF, Steven M.

    IPC: G06F12/14

    CPC classification number: G06F12/145 ,  G06F12/1027 ,  G06F21/52 ,  G06F21/54 ,  G06F21/575 ,  G06F21/629 ,  G06F21/71 ,  G06F21/74 ,  G06F21/79 ,  G06F21/81 ,  G06F2221/2105 ,  G06F2221/2141

    Abstract: Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.

    Abstract translation: 披露了用于防止攻击的方法和系统，该攻击旨在用非真实的，不安全的代码替换经认证的安全代码并使用CPU的存储器管理单元（MMU）中的现有硬件资源。 在某些实施例中，指示存储器中的页面之前已经被认证为安全的许可条目被保持在转换后备缓冲器（TLB）中并且在遇到驻留在外部页面处的指令时被检查。 指示权限的TLB权限条目无效会导致访问页面的按需认证。 在认证时，TLB中的许可条目被更新以反映该页面已被认证。 作为另一个例子，在某些实施例中，当遇到驻留在外部页面的指令时，维护和检查最近认证页面的页面。

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