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    COMMUNICATING TRANSACTION-SPECIFIC ATTRIBUTES IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) SYSTEM
    1.
    发明申请
    COMMUNICATING TRANSACTION-SPECIFIC ATTRIBUTES IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) SYSTEM 审中-公开
    在外围组件互连显式（PCIE）系统中交流交互特定属性

    公开(公告)号：WO2016209568A1

    公开(公告)日：2016-12-29

    申请号：PCT/US2016/035155

    申请日：2016-06-01

    Applicant: QUALCOMM INCORPORATED

    Inventor： ROSENBERG, Ofer ,  GIL, Amit ,  PANIAN, James; Lionel ,  PATEL, Piyush ,  YIFRACH, Shaul; Yohai

    IPC: G06F13/42

    CPC classification number: G06F13/4282 ,  G06F13/1673 ,  G06F13/4022 ,  G06F2213/0026

    Abstract: A PCIe system includes a host system (304) and at least one PCIe endpoint (302). The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. The PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. A PCIe root complex (316) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.

    Abstract translation: PCIe系统包括主机系统（304）和至少一个PCIe端点（302）。 PCIe端点配置为确定可以提高预定义主机事务的效率和性能的一个或多个特定于事务的属性。 PCIe端点对至少一个PCIe TLP的事务层分组（TLP）前缀中的事务特定属性进行编码，并将PCIe TLP提供给主机系统。 主机系统中的PCIe根组合（316）被配置为从PCIe端点接收的PCIe TLP的TLP前缀中检测并提取特定于事务的属性。 通过传递PCIe TLP的TLP前缀中的特定于交易的属性，可以在不违反现有PCIe标准的情况下提高PCIe系统的效率和性能。

    EXTENDED MESSAGE SIGNALED INTERRUPTS (MSI) MESSAGE DATA
    3.
    发明申请
    EXTENDED MESSAGE SIGNALED INTERRUPTS (MSI) MESSAGE DATA 审中-公开
    扩展信息信号中断（MSI）消息数据

    公开(公告)号：WO2016209730A1

    公开(公告)日：2016-12-29

    申请号：PCT/US2016/038120

    申请日：2016-06-17

    Applicant: QUALCOMM INCORPORATED

    Inventor： ROSENBERG, Ofer ,  GIL, Amit ,  PANIAN, James; Lionel ,  PATEL, Piyush ,  YIFRACH, Shaul; Yohai

    IPC: G06F13/24

    CPC classification number: G06F13/24 ,  G06F13/4282

    Abstract: Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.

    Abstract translation: 公开了扩展消息信号中断（MSI）数据。 在一个方面，MSI比特被修改为包括系统级标识符。 在示例性方面，MSI消息数据的高16位被修改为系统级标识符。 通过在MSI消息数据内提供系统级标识符，中断控制器可以验证中断源。

    TRANSLATION OF VIRTUAL ADDRESSES TO PHYSICAL ADDRESSES
    4.
    发明申请
    TRANSLATION OF VIRTUAL ADDRESSES TO PHYSICAL ADDRESSES 审中-公开

    公开(公告)号：WO2019210019A1

    公开(公告)日：2019-10-31

    申请号：PCT/US2019/029044

    申请日：2019-04-25

    Applicant: QUALCOMM INCORPORATED

    Inventor： NORMAN, Jason ,  PATEL, Piyush ,  ANIGUNDI, Rakesh ,  SADAYAN EBRAMSAH MO ABDUL, Sadayan Ghows Ghani

    IPC: G06F12/0808 ,  G06F12/1027

    Abstract: A memory management unit (MMU) is disclosed. The MMU is configured to receive a translation request from a processing system, wherein the translation request specifies a virtual address to be translated, search a page table stored in a physical memory system for a page table entry that specifies the virtual address, receive a translation lookaside buffer invalidation (TLBI) signal from the processing system, wherein the TLBI signal specifies the virtual address, in response to receiving the TLBI signal specifying the virtual address, invalidate a translation lookaside buffer (TLB) entry in a TLB, wherein the invalidated TLB entry specifies the virtual address and restart the search of the page table for the page table entry that specifies the virtual address.

    HARDWARE CO-ORDINATION OF RESOURCE MANAGEMENT IN DISTRIBUTED SYSTEMS
    9.
    发明申请
    HARDWARE CO-ORDINATION OF RESOURCE MANAGEMENT IN DISTRIBUTED SYSTEMS 审中-公开

    公开(公告)号：WO2020185766A1

    公开(公告)日：2020-09-17

    申请号：PCT/US2020/021870

    申请日：2020-03-10

    Applicant: QUALCOMM INCORPORATED

    Inventor： PATEL, Piyush ,  MANN, Kevin ,  HAGGIS, Theodore ,  SINGH, Malvika ,  KUTCHI, Mit

    IPC: G06F9/50

    Abstract: Systems and methods are directed to methods and apparatus for transferring ownership of common resources from a source entity, which owns a resource, to a destination entity, which will own the resource, in a distributed system. The method includes the source entity receiving a command to change ownership (the MOVE command), and then marking the source entity as no longer owning the common resource. The source entity then sends a MOVE command to the destination entity, which will then update its common resource ownership table to reflect that the ownership of the common resource has been transferred from the source entity to the destination entity. It is advantageous that the updating of ownership of the common resource in the source entity occur simultaneously with the dispatching of the MOVE command to the destination entity.

    TRANSACTION DISPATCHER FOR MEMORY MANAGEMENT UNIT
    10.
    发明申请
    TRANSACTION DISPATCHER FOR MEMORY MANAGEMENT UNIT 审中-公开

    公开(公告)号：WO2019060526A1

    公开(公告)日：2019-03-28

    申请号：PCT/US2018/051917

    申请日：2018-09-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： ABDUL, Sadayan Ghows Ghani Sadayan Ebramsah ,  PATEL, Piyush ,  TROMBLEY, Michael ,  ANIGUNDI, Rakesh ,  NORMAN, Jason ,  SEYFRIED, Aaron

    IPC: G06F12/02 ,  G06F12/10 ,  G06F12/1027

    Abstract: According to various aspects, a memory management unit (MMU) having multiple parallel translation machines may collect transactions in an incoming transaction stream and select appropriate transactions to dispatch to the parallel translation machines. For example, the MMU may include a dispatcher that can identify different transactions that belong to the same address set (e.g., have the same address translation) and dispatch one transaction from each transaction set to an individual translation machine. As such, the dispatcher may be used to ensure that multiple parallel translation machines do not perform identical memory translations, as other transactions that share the same address translation may obtain the translation results from a translation lookaside buffer.

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