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    ADDRESS MULTIPLEXING IN PSEUDO-DUAL PORT MEMORY
    12.
    发明申请
    ADDRESS MULTIPLEXING IN PSEUDO-DUAL PORT MEMORY 审中-公开
    地址在双端口存储器中的多路复用

    公开(公告)号：WO2009114288A1

    公开(公告)日：2009-09-17

    申请号：PCT/US2009/035371

    申请日：2009-02-27

    Applicant: QUALCOMM Incorporated ,  JUNG, Changho ,  ZHONG, Cheng

    Inventor： JUNG, Changho ,  ZHONG, Cheng

    IPC: G11C7/22 ,  G11C8/16

    CPC classification number: G11C7/1072 ,  G11C7/22

    Abstract: A pseudo-dual port memory address multiplexing system includes a control circuit (103) operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit (105) monitors a read operation and generates a switching signal (WCLK) when the read operation is determined to be complete. A multiplexer (104) is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time.

    Abstract translation: 伪双端口存储器地址复用系统包括控制电路（103），用于识别在单个时钟周期期间要完成的读取请求和写入请求。 自动时间跟踪电路（105）监视读取操作，并且当读取操作被确定为完成时产生切换信号（WCLK）。 复用器（104）响应于切换信号，用于在适当的时间选择性地向存储器地址单元提供读取地址和写入地址。

    SYSTEM AND METHOD OF SELECTIVELY APPLYING NEGATIVE VOLTAGE TO WORDLINES DURING MEMORY DEVICE READ OPERATION
    13.
    发明申请
    SYSTEM AND METHOD OF SELECTIVELY APPLYING NEGATIVE VOLTAGE TO WORDLINES DURING MEMORY DEVICE READ OPERATION 审中-公开
    在存储器件读取操作期间选择性地将负电压应用于WORDLINES的系统和方法

    公开(公告)号：WO2009089411A1

    公开(公告)日：2009-07-16

    申请号：PCT/US2009/030540

    申请日：2009-01-09

    Applicant: QUALCOMM INCORPORATED ,  YOON, Sei, Seung ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed, H.

    Inventor： YOON, Sei, Seung ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed, H.

    IPC: G11C11/16

    CPC classification number: G11C8/08 ,  G11C11/1673

    Abstract: Systems and methods of selectively applying negative voltage to word lines during memory device read operation are disclosed. In an embodiment, a memory device (100) includes a word line logic circuit (110) coupled to a plurality of word lines (108) and adapted to selectively apply a positive voltage (V) to a selected word line coupled to a selected memory cell that includes a magnetic tunnel junction (MTJ) device and to apply a negative voltage (NV) to unselected word lines.

    Abstract translation: 公开了在存储器件读取操作期间选择性地向字线施加负电压的系统和方法。 在一个实施例中，存储器件（100）包括耦合到多个字线（108）的字线逻辑电路（110），并且适于选择性地将正电压（V）施加到耦合到所选择的存储器的选定字线 包括磁性隧道结（MTJ）装置，并向未选择的字线施加负电压（NV）。

    SYSTEM AND METHOD OF CONDITIONAL CONTROL OF LATCH CIRCUIT DEVICES
    14.
    发明申请
    SYSTEM AND METHOD OF CONDITIONAL CONTROL OF LATCH CIRCUIT DEVICES 审中-公开
    LATCH电路设备的条件控制系统和方法

    公开(公告)号：WO2009089403A1

    公开(公告)日：2009-07-16

    申请号：PCT/US2009/030521

    申请日：2009-01-09

    Applicant: QUALCOMM INCORPORATED ,  RAO, Hari M. ,  ZHONG, Cheng ,  CHEN, Zhiqin

    Inventor： RAO, Hari M. ,  ZHONG, Cheng ,  CHEN, Zhiqin

    IPC: H03K3/037

    CPC classification number: H03K3/037

    Abstract: A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of the output in response to receiving the reset control signal

    Abstract translation: 电路装置包括用于接收复位控制信号的第一输入和耦合到锁存器的输出的第二输入。 电路装置还包括逻辑电路，其适于响应于接收到复位控制信号而基于输出的状态来有条件地重置锁存器

    LOW-POWER HIGH-SPEED CMOS CLOCK GENERATION CIRCUIT
    15.
    发明申请
    LOW-POWER HIGH-SPEED CMOS CLOCK GENERATION CIRCUIT 审中-公开

    公开(公告)号：WO2023048957A1

    公开(公告)日：2023-03-30

    申请号：PCT/US2022/042939

    申请日：2022-09-08

    Applicant: QUALCOMM INCORPORATED

    Inventor： YE, Jianwen ,  SUN, Bo ,  ZHONG, Cheng

    IPC: H03L7/081 ,  H03L7/24

    Abstract: A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

    SYSTEM AND METHOD OF STABILIZING CHARGE PUMP NODE VOLTAGE LEVELS
    17.
    发明申请
    SYSTEM AND METHOD OF STABILIZING CHARGE PUMP NODE VOLTAGE LEVELS 审中-公开
    充电泵节电压水平稳定系统及方法

    公开(公告)号：WO2013071268A2

    公开(公告)日：2013-05-16

    申请号：PCT/US2012/064723

    申请日：2012-11-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： ZHONG, Cheng ,  NAVUBOTHU, Swarna L. ,  DANG, Nam V. ,  KONG, Xiaohua

    CPC classification number: H03L7/0893

    Abstract: A method includes tracking a tuning voltage at a first circuit coupled to a first drain node of a first supply of a charge pump. The method also includes tracking the tuning voltage at a second circuit coupled to a second drain node of a second supply of the charge pump. The method further includes stabilizing a first voltage of the first drain node and a second voltage of the second drain node responsive to the tuning voltage.

    Abstract translation: 一种方法包括在耦合到电荷泵的第一电源的第一漏极节点的第一电路处跟踪调谐电压。 该方法还包括在耦合到电荷泵的第二电源的第二漏极节点的第二电路处跟踪调谐电压。 该方法还包括响应于调谐电压稳定第一漏极节点的第一电压和第二漏极节点的第二电压。

    DIGITALLY-CONTROLLABLE DELAY FOR SENSE AMPLIFIER
    18.
    发明申请
    DIGITALLY-CONTROLLABLE DELAY FOR SENSE AMPLIFIER 审中-公开
    用于感应放大器的数字控制延时

    公开(公告)号：WO2010077611A1

    公开(公告)日：2010-07-08

    申请号：PCT/US2009/066999

    申请日：2009-12-07

    Applicant: QUALCOMM INCORPORATED ,  PARK, Dongkyu ,  DAVIERWALLA, Anosh B. ,  ZHONG, Cheng ,  ABU-RAHMA, Mohamed Hassan Soliman ,  YOON, Sei Seung

    Inventor： PARK, Dongkyu ,  DAVIERWALLA, Anosh B. ,  ZHONG, Cheng ,  ABU-RAHMA, Mohamed Hassan Soliman ,  YOON, Sei Seung

    IPC: G11C7/06 ,  G11C7/22 ,  G11C11/16

    CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2207/065 ,  G11C2207/2281

    Abstract: Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. A circuit includes a sense amplifier (160), having a first input (162), a second input (164), and an enable input (166); a first amplifier (132) coupled to an output of a magnetic resistance-based memory cell (112); a second amplifier (134) coupled to a reference output of the cell; and a digitally-controllable amplifier (136) coupled to a tracking circuit cell (116) that is similar to the cell of the MRAM. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit (150). The sense amplifier may generate an output value based on the amplified values received from the output of the magnetic resistance-based memory cell and the reference cell once the sense amplifier receives an enable signal (152) from the digitally-controllable amplifier via the logic circuit.

    Abstract translation: 公开了在读取磁随机存取存储器（MRAM）装置中插入可选延迟的电路，装置和方法。 电路包括具有第一输入（162），第二输入（164）和使能输入（166）的读出放大器（160）。 耦合到基于磁阻的存储单元（112）的输出端的第一放大器（132）; 耦合到所述单元的参考输出的第二放大器（134） 以及耦合到类似于MRAM的单元的跟踪电路单元（116）的数字可控放大器（136）。 读出放大器的第一输入耦合到第一放大器，读出放大器的第二输入耦合到第二放大器，而使能输入经由逻辑电路（150）耦合到第三数字可控放大器。 一旦感测放大器从数字可控放大器经由逻辑电路接收到使能信号（152），读出放大器可以基于从基于磁阻的存储单元和参考单元的输出接收的放大值来产生输出值 。

    MEMORY DEVICE FOR RESISTANCE-BASED MEMORY APPLICATIONS
    19.
    发明申请
    MEMORY DEVICE FOR RESISTANCE-BASED MEMORY APPLICATIONS 审中-公开
    用于基于电阻的存储器应用的存储器件

    公开(公告)号：WO2010030531A1

    公开(公告)日：2010-03-18

    申请号：PCT/US2009/055617

    申请日：2009-09-01

    Applicant: QUALCOMM INCORPORATED ,  DAVIERWALLA, Anosh B. ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed Hassan ,  SANI, Mehdi Hamidi ,  YOON, Sei Seung

    Inventor： DAVIERWALLA, Anosh B. ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed Hassan ,  SANI, Mehdi Hamidi ,  YOON, Sei Seung

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C11/16

    CPC classification number: G11C11/1673

    Abstract: In a particular embodiment, a memory device (100) is disclosed that includes a memory cell (226) including a resistance based memory element (228) coupled to an access transistor (230). The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier (202) configured to couple the memory cell to a supply voltage (Vamp) that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor (216) that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.

    Abstract translation: 在特定实施例中，公开了一种包括存储单元（226）的存储器件（100），该存储器单元包括耦合到存取晶体管（230）的基于电阻的存储元件（228）。 存取晶体管具有第一氧化物厚度，以使得能够在工作电压下操作存储单元。 存储器件还包括被配置为将存储器单元耦合到大于电压限制的电源电压（Vamp）的第一放大器（202），以基于通过存储器单元的电流产生数据信号。 第一放大器包括具有大于第一氧化物厚度的第二氧化物厚度的钳位晶体管（216）。 钳位晶体管被配置为防止存储器单元处的工作电压超过电压限制。

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