公开(公告)号：WO2014182556A1

公开(公告)日：2014-11-13

申请号：PCT/US2014/036524

申请日：2014-05-02

Applicant: QUALCOMM INCORPORATED

Inventor： ZUO, Chengjie ,  KIM, Daeik, D. ,  LAN, Je-Hsiung ,  KIM, Jonghae ,  VELEZ, Mario, Francisco ,  YUN, Changhan ,  BERDY, David, F. ,  MIKULKA, Robert, P. ,  NOWAK, Matthew, M. ,  ZHANG, Xiangdong ,  SEE, Puay, H.

IPC: H03H7/46

CPC classification number: H03H7/461 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  Y10T29/49016

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

Abstract translation: 公开了三维（3D）集成电路（IC）（3DIC）中的可调谐双工器。 在一个实施例中，可调谐双工器可以通过在双工器中提供变容二极管或可变电感器之一来形成。 可变电抗器或可变电感器的可变特性允许调谐双工器中的陷波，以便选择频带停止以消除期望频率处的谐波以及控制通带的截止频率。 通过将双工器的元件堆叠成三维空间是保守的，并且可以使用各种变容二极管和电感器。

公开(公告)号：WO2014150747A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/024118

申请日：2014-03-12

Applicant: QUALCOMM INCORPORATED

Inventor： LAN, Je-Hsiung ,  ZUO, Chengjie ,  YUN, Changhan ,  BERDY, David F. ,  KIM, Daeik D. ,  MIKULKA, Robert P. ,  VELEZ, Mario Francisco ,  KIM, Jonghae

IPC: H01L23/498 ,  H01F17/00

CPC classification number: H01L28/40 ,  G06F17/5068 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L27/016 ,  H01L27/12 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.

Abstract translation: 在特定实施例中，器件包括衬底，至少部分延伸穿过衬底的通孔和电容器。 电容器的电介质位于电容器的通孔和板之间，并且电容器的板在衬底外部和器件内部。

公开(公告)号：EP2745399B1

公开(公告)日：2019-07-10

申请号：EP12753636.5

申请日：2012-08-20

Applicant: Qualcomm Incorporated

Inventor： ZUO, Chengjie ,  Yun, Changhan ,  KIM, Jonghae

IPC: H03H9/02 ,  H01L41/18

公开(公告)号：EP3497721A1

公开(公告)日：2019-06-19

申请号：EP17742909.9

申请日：2017-07-11

Applicant: Qualcomm Incorporated

Inventor： ZUO, Chengjie ,  YUN, Changhan Hobie ,  BERDY, David Francis ,  MUDAKATTE, Niranjan Sunil ,  VELEZ, Mario Francisco ,  GU, Shiqun ,  KIM, Jonghae

IPC: H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00

公开(公告)号：EP3488467A1

公开(公告)日：2019-05-29

申请号：EP17735704.3

申请日：2017-06-20

Applicant: Qualcomm Incorporated

Inventor： YUN, Changhan ,  ZUO, Chengjie ,  VELEZ, Mario ,  MUDAKATTE, Niranjan Sunil ,  GU, Shiqun ,  KIM, Jonghae ,  BERDY, David

IPC: H01L23/522 ,  H01L23/64 ,  H01L21/60 ,  H05K1/16 ,  H05K1/18 ,  H05K3/46 ,  H01F17/00 ,  H04B1/00

公开(公告)号：EP3400609A1

公开(公告)日：2018-11-14

申请号：EP16791761.6

申请日：2016-10-26

Applicant: Qualcomm Incorporated

Inventor： KIM, Daeik Daniel ,  BERDY, David Francis ,  ZUO, Chengjie ,  YUN, Changhan Hobie ,  KIM, Jonghae

IPC: H01L27/02 ,  H01F17/00 ,  H01L23/522 ,  H01L49/02 ,  H01F27/28

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F41/041 ,  H01L23/5222 ,  H01L23/5227 ,  H01L27/0207 ,  H01L28/10 ,  H04B1/40

Abstract: A skewed, co-spiral inductor structure may include a first trace arranged in a first spiral pattern that is supported by a substrate. The skewed, co-spiral inductor structure may also include a second trace arranged in a second spiral pattern, in which the second trace is coupled to the first trace. The first trace may overlap with the second trace in orthogonal overlap areas. In addition, each orthogonal overlap area may have a size defined by a width of the first trace and the width of the second trace. Also, parallel edges of the first trace and the second trace may be arranged to coincide.

公开(公告)号：EP3378160A1

公开(公告)日：2018-09-26

申请号：EP16816120.6

申请日：2016-12-05

Applicant: Qualcomm Incorporated

Inventor： YUN, Changhan Hobie ,  KIM, Daeik Daniel ,  VELEZ, Mario Francisco ,  ZUO, Chengjie ,  BERDY, David Francis ,  KIM, Jonghae

IPC: H03H7/46

CPC classification number: H01P5/16 ,  H01Q1/22 ,  H01Q1/50 ,  H03H7/0115 ,  H03H7/463

Abstract: A multiplexer structure includes a passive substrate. The multiplexer structure may also include a high band filter on the passive substrate. The high band filter may include a 2D planar spiral inductor(s) on the passive substrate. The multiplexer structure may further include a low band filter on the passive substrate. The low band filter may include a 3D through-substrate inductor and a first capacitor(s) on the passive substrate. The multiplexer structure may also include a through substrate via(s) coupling the high band filter and the low band filter.

公开(公告)号：EP3005559B1

公开(公告)日：2017-12-13

申请号：EP14724235.8

申请日：2014-03-25

Applicant: Qualcomm Incorporated

Inventor： ZUO, Chengjie ,  KIM, Jonghae ,  YUN, Changhan Hobie ,  KIM, Daeik Daniel ,  VELEZ, Mario Francisco ,  LAN, Je-Hsiung ,  MIKULKA, Robert Paul ,  NOWAK, Matthew Michael

IPC: H03H7/01

CPC classification number: H03H7/0138 ,  H03H7/0115 ,  Y10T29/417

公开(公告)号：EP3161841A1

公开(公告)日：2017-05-03

申请号：EP15745597.3

申请日：2015-06-04

Applicant: Qualcomm Incorporated

Inventor： KIM, Daeik Daniel ,  YUN, Changhan Hobie ,  VELEZ, Mario Francisco ,  ZUO, Chengjie ,  BERDY, David Francis ,  KIM, Jonghae

IPC: H01F17/00 ,  H01L49/02 ,  H01L23/64

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F41/04 ,  H01F2017/002 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01L23/15 ,  H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  Y10T29/49075 ,  H01L2924/00

Abstract: Methods and apparatuses, wherein the method forms a first plurality of vias in a substrate, further comprising forming the first plurality of vias to be substantially the same height. The method forms a plurality of conductive traces external to the substrate and couples the plurality of conductive traces to the first plurality of vias: wherein the plurality of conductive traces and the first plurality of vias comprise a plurality of conductive turns and wherein the plurality of conductive turns are in a spiral configuration substantially within a first plane.

Abstract translation: 其中所述方法在衬底中形成第一多个通孔的方法和装置进一步包括将所述第一多个通孔形成为基本上相同的高度。 该方法在衬底外部形成多个导电迹线并将多个导电迹线耦合到第一多个通孔：其中多个导电迹线和第一多个通孔包括多个导电匝，并且其中多个导电迹线 匝基本上处于第一平面内的螺旋构造。

公开(公告)号：EP3095120A1

公开(公告)日：2016-11-23

申请号：EP14827641.3

申请日：2014-12-17

Applicant: Qualcomm Incorporated

Inventor： KIM, Daeik, Daniel ,  KIM, Jonghae ,  ZUO, Chengjie ,  VELEZ, Mario, Francisco ,  YUN, Changhan, Hobie

IPC: H01F27/28

CPC classification number: H01F41/041 ,  H01F27/2804 ,  H01F41/00 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01L2924/0002 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.