公开(公告)号：WO2023014488A1

公开(公告)日：2023-02-09

申请号：PCT/US2022/037358

申请日：2022-07-15

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Jonghae ,  PARK, Sang-June ,  CHIDAMBARAM, Periannan

IPC: H03H7/48 ,  H01P5/16

Abstract: An aspect relates to a signal power splitter/combiner (700) including a first signal port (Pl); a first resistor (RO); a first impedance transformer (710) coupled in series with the first resistor between the first signal port and a first intermediate node (nl); a second impedance transformer (720) coupled between the first intermediate node (nl) and a second signal port (P2); a third impedance transformer (730) coupled between the first intermediate (nl) node and a third signal port (P3); and a second resistor (R2) coupled between the second and third signal ports. The signal power splitter/ combiner may further include a fourth impedance transformer (740) coupled between the second impedance (720) transformer and the second signal port, a fifth impedance transformer (750) coupled between the third impedance transformer (730) and the third signal port; and a third resistor (Rl) coupled between a third intermediate node (n3) and a second intermediate node (n2); the second intermediate node (n2) between the second and fourth impedance transformers (720,740) and the third intermediate node (n3) between the third and fifth impedance transformers (730,750).

公开(公告)号：WO2022191919A1

公开(公告)日：2022-09-15

申请号：PCT/US2022/012346

申请日：2022-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Jonghae ,  YUN, Changhan Hobie ,  LAN, Je-Hsiung ,  DUTTA, Ranadeep

IPC: H01F17/00 ,  H01L49/02

Abstract: An inductor includes a first metallization layer multi-turn trace. The inductor also includes a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via. The inductor further includes a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias.

公开(公告)号：WO2022055598A1

公开(公告)日：2022-03-17

申请号：PCT/US2021/039621

申请日：2021-06-29

Applicant: QUALCOMM INCORPORATED

Inventor： CHAVA, Bharani ,  SONG, Stanley, Seungchul ,  ROY, Abinash ,  KIM, Jonghae

IPC: H01L25/16 ,  H01L25/065 ,  H01L23/528 ,  H01L21/98 ,  H01L25/18

Abstract: An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.

公开(公告)号：WO2021216382A1

公开(公告)日：2021-10-28

申请号：PCT/US2021/027829

申请日：2021-04-16

Applicant: QUALCOMM INCORPORATED

Inventor： LAN, Je-Hsiung ,  DUTTA, Ranadeep ,  KIM, Jonghae

IPC: H03H9/05 ,  H03H9/10 ,  H03H9/02 ,  H03H9/17 ,  H03H3/02 ,  H01L29/20

Abstract: A 3D integrated circuit (3D IC) chip (400) is described. The 3D IC chip includes a die (440) having a compound semiconductor high electron mobility transistor (HEMT) active device (410). The compound semiconductor HEMT active device is composed of compound semiconductor layers (420) on a single crystal, compound semiconductor layer (442). The 3D IC chip also includes an acoustic device (430) integrated in the single crystal, compound semiconductor layer (442). The 3D IC chip further includes a passive device (460) integrated in back-end-of-line layers (450) of the die on the single crystal, compound semiconductor layer.

公开(公告)号：WO2021183506A1

公开(公告)日：2021-09-16

申请号：PCT/US2021/021495

申请日：2021-03-09

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Jonghae ,  SHAH, Milind ,  CHIDAMBARAM, Periannan

IPC: H01L23/538

Abstract: A device that includes a first package and a second package coupled to the first package. The first package includes a first integrated device, a first encapsulation layer encapsulating the first integrated device, a plurality of vias traveling through the first encapsulation layer, a first redistribution portion comprising a first plurality of redistribution interconnects, wherein the first redistribution portion is coupled to the first encapsulation layer, and a first plurality of contacts coupled to the first integrated device. The second package includes a passive device, a second encapsulation layer encapsulating the passive device, a second redistribution portion comprising a second plurality of redistribution interconnects, wherein the second redistribution portion is coupled to the passive device and the second encapsulation layer, and a second plurality of contacts coupled to the passive device, wherein the second plurality of contacts is coupled to the first plurality of contacts from the first package.

公开(公告)号：WO2018057351A1

公开(公告)日：2018-03-29

申请号：PCT/US2017/051186

申请日：2017-09-12

Applicant: QUALCOMM INCORPORATED

Inventor： ZUO, Chengjie ,  KIM, Jonghae ,  BERDY, David Francis ,  YUN, Changhan Hobie ,  MUDAKATTE, Niranjan Sunil ,  VELEZ, Mario Francisco ,  GU, Shiqun

IPC: H01L23/552 ,  H01L23/31

CPC classification number: H01L27/01 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49805 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/1815 ,  H01L2924/19011 ,  H01L2924/3025 ,  H03H7/0115 ,  H03H7/468 ,  H04B1/0057 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated circuit (IC) device includes a die having an integrated passive device (IPD) layer. The integrated circuit device also includes a substrate supporting the die, a molding compound surrounding the die. The integrated circuit device further includes a backside conductive layer on a surface of the die that is distal from the IPD layer. The integrated circuit device also includes vias coupling the backside conductive layer to a ground plane through the molding compound.

Abstract translation: 集成电路（IC）器件包括具有集成无源器件（IPD）层的管芯。 集成电路器件还包括支撑管芯的衬底，围绕管芯的模制化合物。 集成电路器件进一步包括位于远离IPD层的管芯表面上的背侧导电层。 集成电路器件还包括通过模塑料将背面导电层耦合到接地平面的通孔。

公开(公告)号：WO2018044543A1

公开(公告)日：2018-03-08

申请号：PCT/US2017/046793

申请日：2017-08-14

Applicant: QUALCOMM INCORPORATED

Inventor： VELEZ, Mario ,  MUDAKATTE, Niranjan Sunil ,  YUN, Changhan ,  BERDY, David ,  GU, Shiqun ,  KIM, Jonghae ,  ZUO, Chengjie

IPC: H01L23/64 ,  H02M3/00

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L28/10 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19042 ,  H01L2924/19102 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A device that includes a single substrate layer, a plurality of interconnects over the single substrate layer, the plurality of interconnects configured to operate as at least one passive component, a first die coupled to the single substrate layer and the plurality of interconnects, and an encapsulation layer that at least partially encapsulates the first die and the plurality of interconnects configured to operate as at least one passive component. In some implementations, the single substrate layer, the first die and the encapsulation layer comprise an overall thickness of about 225 microns (μm) or less. In some implementations, the single substrate layer comprises a thickness of about 75 microns (μm) or less.

Abstract translation: 包括单个衬底层，在单个衬底层上的多个互连，多个互连配置为作为至少一个无源部件操作的器件，耦合到单个衬底层的第一管芯 所述多个互连以及至少部分地封装所述第一管芯和所述多个互连的封装层，所述封装层被配置为作为至少一个无源组件进行操作。 在一些实施方式中，单个衬底层，第一管芯和封装层包括约225微米（μm）或更小的总厚度。 在一些实施方式中，单个基底层包括约75微米（μm）或更小的厚度。

公开(公告)号：WO2018026447A1

公开(公告)日：2018-02-08

申请号：PCT/US2017/039262

申请日：2017-06-26

Applicant: QUALCOMM INCORPORATED

Inventor： BERDY, David, Francis ,  YUN, Changhan, Hobie ,  ZUO, Chengjie ,  MUDAKATTE, Niranjan, Sunil ,  VELEZ, Mario, Francisco ,  GU, Shiqun ,  KIM, Jonghae

IPC: H05K1/02 ,  H05K1/14 ,  H01L23/64

Abstract: An integrated circuit device includes a first substrate having a ground plane. The integrated circuit device also includes a second substrate. The second substrate has a first layer of passive devices. The passive devices include at least one inductor on a first side of the second substrate. The first layer of passive devices is substantially orthogonal to the ground plane and the second substrate supported by the first substrate. An inductor magnetic field is substantially parallel to the ground plane.

Abstract translation: 集成电路器件包括具有接地平面的第一基板。 集成电路器件还包括第二衬底。 第二衬底具有第一层无源器件。 无源器件在第二衬底的第一侧上包括至少一个电感器。 第一层无源器件与接地平面和第一衬底支撑的第二衬底基本正交。 电感磁场基本上与地平面平行。

公开(公告)号：WO2017116616A1

公开(公告)日：2017-07-06

申请号：PCT/US2016/064962

申请日：2016-12-05

Applicant: QUALCOMM INCORPORATED

Inventor： YUN, Changhan Hobie ,  KIM, Daeik Daniel ,  VELEZ, Mario Francisco ,  ZUO, Chengjie ,  BERDY, David Francis ,  KIM, Jonghae

IPC: H03H7/46

CPC classification number: H01P5/16 ,  H01Q1/22 ,  H01Q1/50 ,  H03H7/0115 ,  H03H7/463

Abstract: A multiplexer structure (500) includes a passive substrate (508). The multiplexer structure (500) may also include a high band filter (502) on the passive substrate. The high band filter (502) may include a 2D planar spiral inductor(s) (530, 540) on the passive substrate. The multiplexer structure (500) may further include a low band filter (504) on the passive substrate. The low band filter (504) may include a 3D through-substrate inductor (510, 520) and a first capacitor(s) on the passive substrate. The multiplexer structure (500) may also include a through substrate via(s) (VIA) coupling the high band filter (502) and the low band filter (504).

Abstract translation: 多路复用器结构（500）包括无源衬底（508）。 多路复用器结构（500）还可以包括无源衬底上的高频带滤波器（502）。 高带滤波器（502）可以包括无源衬底上的2D平面螺旋电感器（530,540）。 多路复用器结构（500）可以进一步包括在无源衬底上的低频带滤波器（504）。 低带滤波器（504）可以包括无源衬底上的3D贯穿衬底电感器（510,520）和第一电容器。 多路复用器结构（500）还可以包括耦合高频带滤波器（502）和低频带滤波器（504）的贯穿衬底通孔（VIA）。

公开(公告)号：WO2017112397A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/064968

申请日：2016-12-05

Applicant: QUALCOMM INCORPORATED

Inventor： BERDY, David Francis ,  KIM, Daeik Daniel ,  MUDAKATTE, Niranjan Sunil ,  LAN, Je-Hsiung Jeffrey ,  ZUO, Chengjie ,  YUN, Changhan Hobie ,  VELEZ, Mario Francisco ,  KIM, Jonghae

IPC: H01L23/522 ,  H01L27/08 ,  H01L49/02 ,  H01G4/33 ,  H01L29/94

CPC classification number: H01G4/30 ,  H01G4/01 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/86 ,  H01L28/87 ,  H01L29/94

Abstract: An exemplary MIM capacitor may include a first metal plate, a dielectric layer on the first metal plate, a second metal plate on the dielectric layer, a via layer on the second metal plate, and a third metal plate on the via layer where the second metal plate has a tapered outline with a first side and a second side longer than the first side such that the second side provides a lower resistance path for a current flow.

Abstract translation: 示例性MIM电容器可以包括第一金属板，第一金属板上的电介质层，电介质层上的第二金属板，第二金属板上的通孔层以及第三金属 其中第二金属板具有带第一侧和比第一侧长的第二侧的锥形轮廓，使得第二侧为电流提供较低的电阻路径。