公开(公告)号：WO2018057351A1

公开(公告)日：2018-03-29

申请号：PCT/US2017/051186

申请日：2017-09-12

Applicant: QUALCOMM INCORPORATED

Inventor： ZUO, Chengjie ,  KIM, Jonghae ,  BERDY, David Francis ,  YUN, Changhan Hobie ,  MUDAKATTE, Niranjan Sunil ,  VELEZ, Mario Francisco ,  GU, Shiqun

IPC: H01L23/552 ,  H01L23/31

CPC classification number: H01L27/01 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49805 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/1815 ,  H01L2924/19011 ,  H01L2924/3025 ,  H03H7/0115 ,  H03H7/468 ,  H04B1/0057 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated circuit (IC) device includes a die having an integrated passive device (IPD) layer. The integrated circuit device also includes a substrate supporting the die, a molding compound surrounding the die. The integrated circuit device further includes a backside conductive layer on a surface of the die that is distal from the IPD layer. The integrated circuit device also includes vias coupling the backside conductive layer to a ground plane through the molding compound.

Abstract translation: 集成电路（IC）器件包括具有集成无源器件（IPD）层的管芯。 集成电路器件还包括支撑管芯的衬底，围绕管芯的模制化合物。 集成电路器件进一步包括位于远离IPD层的管芯表面上的背侧导电层。 集成电路器件还包括通过模塑料将背面导电层耦合到接地平面的通孔。

公开(公告)号：WO2018044543A1

公开(公告)日：2018-03-08

申请号：PCT/US2017/046793

申请日：2017-08-14

Applicant: QUALCOMM INCORPORATED

Inventor： VELEZ, Mario ,  MUDAKATTE, Niranjan Sunil ,  YUN, Changhan ,  BERDY, David ,  GU, Shiqun ,  KIM, Jonghae ,  ZUO, Chengjie

IPC: H01L23/64 ,  H02M3/00

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L28/10 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19042 ,  H01L2924/19102 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A device that includes a single substrate layer, a plurality of interconnects over the single substrate layer, the plurality of interconnects configured to operate as at least one passive component, a first die coupled to the single substrate layer and the plurality of interconnects, and an encapsulation layer that at least partially encapsulates the first die and the plurality of interconnects configured to operate as at least one passive component. In some implementations, the single substrate layer, the first die and the encapsulation layer comprise an overall thickness of about 225 microns (μm) or less. In some implementations, the single substrate layer comprises a thickness of about 75 microns (μm) or less.

Abstract translation: 包括单个衬底层，在单个衬底层上的多个互连，多个互连配置为作为至少一个无源部件操作的器件，耦合到单个衬底层的第一管芯 所述多个互连以及至少部分地封装所述第一管芯和所述多个互连的封装层，所述封装层被配置为作为至少一个无源组件进行操作。 在一些实施方式中，单个衬底层，第一管芯和封装层包括约225微米（μm）或更小的总厚度。 在一些实施方式中，单个基底层包括约75微米（μm）或更小的厚度。

公开(公告)号：WO2018026447A1

公开(公告)日：2018-02-08

申请号：PCT/US2017/039262

申请日：2017-06-26

Applicant: QUALCOMM INCORPORATED

Inventor： BERDY, David, Francis ,  YUN, Changhan, Hobie ,  ZUO, Chengjie ,  MUDAKATTE, Niranjan, Sunil ,  VELEZ, Mario, Francisco ,  GU, Shiqun ,  KIM, Jonghae

IPC: H05K1/02 ,  H05K1/14 ,  H01L23/64

Abstract: An integrated circuit device includes a first substrate having a ground plane. The integrated circuit device also includes a second substrate. The second substrate has a first layer of passive devices. The passive devices include at least one inductor on a first side of the second substrate. The first layer of passive devices is substantially orthogonal to the ground plane and the second substrate supported by the first substrate. An inductor magnetic field is substantially parallel to the ground plane.

Abstract translation: 集成电路器件包括具有接地平面的第一基板。 集成电路器件还包括第二衬底。 第二衬底具有第一层无源器件。 无源器件在第二衬底的第一侧上包括至少一个电感器。 第一层无源器件与接地平面和第一衬底支撑的第二衬底基本正交。 电感磁场基本上与地平面平行。

公开(公告)号：WO2017116616A1

公开(公告)日：2017-07-06

申请号：PCT/US2016/064962

申请日：2016-12-05

Applicant: QUALCOMM INCORPORATED

Inventor： YUN, Changhan Hobie ,  KIM, Daeik Daniel ,  VELEZ, Mario Francisco ,  ZUO, Chengjie ,  BERDY, David Francis ,  KIM, Jonghae

IPC: H03H7/46

CPC classification number: H01P5/16 ,  H01Q1/22 ,  H01Q1/50 ,  H03H7/0115 ,  H03H7/463

Abstract: A multiplexer structure (500) includes a passive substrate (508). The multiplexer structure (500) may also include a high band filter (502) on the passive substrate. The high band filter (502) may include a 2D planar spiral inductor(s) (530, 540) on the passive substrate. The multiplexer structure (500) may further include a low band filter (504) on the passive substrate. The low band filter (504) may include a 3D through-substrate inductor (510, 520) and a first capacitor(s) on the passive substrate. The multiplexer structure (500) may also include a through substrate via(s) (VIA) coupling the high band filter (502) and the low band filter (504).

Abstract translation: 多路复用器结构（500）包括无源衬底（508）。 多路复用器结构（500）还可以包括无源衬底上的高频带滤波器（502）。 高带滤波器（502）可以包括无源衬底上的2D平面螺旋电感器（530,540）。 多路复用器结构（500）可以进一步包括在无源衬底上的低频带滤波器（504）。 低带滤波器（504）可以包括无源衬底上的3D贯穿衬底电感器（510,520）和第一电容器。 多路复用器结构（500）还可以包括耦合高频带滤波器（502）和低频带滤波器（504）的贯穿衬底通孔（VIA）。

公开(公告)号：WO2017112397A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/064968

申请日：2016-12-05

Applicant: QUALCOMM INCORPORATED

Inventor： BERDY, David Francis ,  KIM, Daeik Daniel ,  MUDAKATTE, Niranjan Sunil ,  LAN, Je-Hsiung Jeffrey ,  ZUO, Chengjie ,  YUN, Changhan Hobie ,  VELEZ, Mario Francisco ,  KIM, Jonghae

IPC: H01L23/522 ,  H01L27/08 ,  H01L49/02 ,  H01G4/33 ,  H01L29/94

CPC classification number: H01G4/30 ,  H01G4/01 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/86 ,  H01L28/87 ,  H01L29/94

Abstract: An exemplary MIM capacitor may include a first metal plate, a dielectric layer on the first metal plate, a second metal plate on the dielectric layer, a via layer on the second metal plate, and a third metal plate on the via layer where the second metal plate has a tapered outline with a first side and a second side longer than the first side such that the second side provides a lower resistance path for a current flow.

Abstract translation: 示例性MIM电容器可以包括第一金属板，第一金属板上的电介质层，电介质层上的第二金属板，第二金属板上的通孔层以及第三金属 其中第二金属板具有带第一侧和比第一侧长的第二侧的锥形轮廓，使得第二侧为电流提供较低的电阻路径。

公开(公告)号：WO2016137733A1

公开(公告)日：2016-09-01

申请号：PCT/US2016/016996

申请日：2016-02-08

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Daeik Daniel ,  YUN, Changhan Hobie ,  VELEZ, Mario Francisco ,  BERDY, David Francis ,  ZUO, Chengjie ,  KIM, Jonghae ,  NOWAK, Matthew Michael

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/60 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/00 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.

Abstract translation: 接地屏蔽通过具有导电表面的导体屏蔽来实现，导电表面立即围绕多芯片模块或器件（例如具有倒装芯片（FC）凸块的多芯片模块或器件）中的单个芯片。 多芯片模块或设备内的单个芯片之间的模块间屏蔽通过由紧邻每个芯片的导体屏蔽表面提供的电磁或射频信号（RF）隔离来实现。 导体屏蔽件直接连接到基板或插入件的一个或多个接地导体部分，以确保可靠的接地。

公开(公告)号：WO2016048629A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/048597

申请日：2015-09-04

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Daeik Daniel ,  LAN, Je-Hsiung Jeffrey ,  YUN, Changhan Hobie ,  VELEZ, Mario Francisco ,  ZUO, Chengjie ,  KIM, Jonghae ,  BERDY, David Francis

IPC: H01L23/00

CPC classification number: H05K1/0271 ,  C23F1/02 ,  H01L21/768 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/09 ,  H05K2201/0154 ,  H05K2201/0195 ,  H01L2924/00

Abstract: A device includes a stress relief region between at least two stress domains of a substrate (e.g., of a semiconductor die or other integrated circuit). The stress relief region includes a conductive structure electrically coupling circuitries of the stress domains between which the conductive structure is disposed.

Abstract translation: 器件包括在衬底（例如，半导体管芯或其他集成电路）的至少两个应力结构域之间的应力消除区域。 应力消除区域包括导电结构，电耦合应力区域的电路，导电结构设置在该应力区域之间。

公开(公告)号：WO2015126640A1

公开(公告)日：2015-08-27

申请号：PCT/US2015/014895

申请日：2015-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： VELEZ, Mario Francisco ,  KIM, Daeik Daniel ,  SONG, Young Kyu ,  ZHANG, Xiaonan ,  KIM, Jonghae ,  YUN, Changhan Hobie ,  ZUO, Chengjie

IPC: H01L23/13 ,  H01L23/498 ,  H01F17/00 ,  H01L49/02

CPC classification number: H05K1/182 ,  H01F17/0006 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/10 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/165 ,  H05K3/4038 ,  H05K2201/10015 ,  H05K2201/10242 ,  H05K2201/10984 ,  Y10T29/49165

Abstract: A low-profile passive-on-package is provided that includes a plurality of recesses that receive corresponding interconnects. Because of the receipt of the interconnects in the recesses, the passive-on-package has a height that is less than a sum of a thickness for the substrate and an interconnect height or diameter.

Abstract translation: 提供了一种低调无源封装，其包括接收相应互连的多个凹槽。 由于在凹槽中接收到互连，所以被动封装的高度小于衬底的厚度和互连高度或直径的总和。

公开(公告)号：WO2015120375A1

公开(公告)日：2015-08-13

申请号：PCT/US2015/014995

申请日：2015-02-09

Applicant: QUALCOMM INCORPORATED

Inventor： YUN, Changhan Hobie ,  KIM, Daeik Daniel ,  ZUO, Chengjie ,  KIM, Jonghae ,  VELEZ, Mario Francisco ,  KIDWELL, JR., Donald William ,  LASITER, Jon Bradley ,  LAI, Kwan-Yu ,  KIM, Jitae ,  SHENOY, Ravindra Vaman

IPC: H01L49/02 ,  H01G4/33 ,  H01G4/012 ,  H01L21/48 ,  H01L27/12

CPC classification number: H01L28/90 ,  H01G4/012 ,  H01G4/33 ,  H01L21/28282 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/12 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.

Abstract translation: 提供的空间效率电容器具有比传统设计更高的品质因数，并且改善了从直通玻璃通孔（TGV）到电介质的电能的耦合。 例如，提供了具有非矩形横截面的TGV，其中TGV的一端耦合到第一金属板。 在第一金属板上形成电介质材料。 第二金属板以与第一金属板的至少一部分重叠以形成电介质材料的至少一个重叠区域的方式形成在电介质材料上。 重叠区域的周边的至少一部分是非平面的。 重叠区域可以形成为环形的多个部分中的大致四分之一环形的闭环形状和/或大致一半的环形形状。

公开(公告)号：WO2014193525A1

公开(公告)日：2014-12-04

申请号：PCT/US2014/031779

申请日：2014-03-25

Applicant: QUALCOMM INCORPORATED

Inventor： ZUO, Chengjie ,  KIM, Jonghae ,  YUN, Changhan Hobie ,  KIM, Daeik Daniel ,  VELEZ, Mario Francisco ,  LAN, Je-Hsiung ,  MIKULKA, Robert Paul ,  NOWAK, Matthew Michael

IPC: H03H7/01

CPC classification number: H03H7/0138 ,  H03H7/0115 ,  Y10T29/417

Abstract: A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution.

Abstract translation: 滤光器包括具有通过基板通孔的玻璃基板。 滤波器还包括由玻璃基板支撑的电容器。 电容器可以具有小于打印分辨率的宽度和/或厚度。 滤波器还包括衬底内的3D电感器。 3D电感器包括耦合到贯穿衬底通孔的玻璃衬底的第一表面上的第一组迹线。 3D电感器还包括耦合到贯通衬底通孔的相对端的玻璃衬底的第二表面上的第二组迹线。 玻璃基板的第二表面与玻璃基板的第一表面相对。 直通衬底通孔和迹线作为3D电感器工作。 第一组迹线和第二组迹线也可以具有小于打印分辨率的宽度和/或厚度。