公开(公告)号：FI822749L

公开(公告)日：1983-02-15

申请号：FI822749

申请日：1982-08-06

Applicant: RCA CORP

Inventor： CHRISTOPHER LAUREN ANN

IPC: H03H17/06 ,  H03H

Abstract: A controllable shift matrix has inputs and outputs and is responsive to bits of an input signal word X(n) at the inputs of ascending order from a least significant bit position to a most significant bit position for controllably producing an output (weighted X(n) the outputs in which the input signal bits may occupy respectively different bit positions. The matrix comprises a plurality of sections (80-88) including at least one divide-by section (82) coupled between the inputs and outputs and including controlled switch means responsive to control signals (C1 ,C1) for selectively passing bits on divide-by input lines to divide-by output lines of the same order as said divide-by input line bit position, or transferring said divide-by input line bits to respective ones of said divide-by output lines which are more than one bit position lower in order than divide-by input line bit positions. A weighting function circuit comprises two such matrices which commonly receive the input word for shifting it in different ways, and a combining circuit for combining the shifted words produced by the matrices to produce a weighted word (Fig. 2 not shown). A digital filter comprises the weighting function circuit allowing reduced complexity and higher speed in coefficient multiplication.

公开(公告)号：FI822750A0

公开(公告)日：1982-08-06

申请号：FI822750

申请日：1982-08-06

Applicant: RCA CORP

Inventor： CHRISTOPHER LAUREN ANN ,  STECKLER STEVEN ALAN

IPC: H03H17/06 ,  H03H

公开(公告)号：IT1159084B

公开(公告)日：1987-02-25

申请号：IT2285782

申请日：1982-08-13

Applicant: RCA CORP

Inventor： CHRISTOPHER LAUREN ANN

IPC: H03H17/06 ,  H03H

Abstract: A controllable shift matrix has inputs and outputs and is responsive to bits of an input signal word X(n) at the inputs of ascending order from a least significant bit position to a most significant bit position for controllably producing an output (weighted X(n) the outputs in which the input signal bits may occupy respectively different bit positions. The matrix comprises a plurality of sections (80-88) including at least one divide-by section (82) coupled between the inputs and outputs and including controlled switch means responsive to control signals (C1 ,C1) for selectively passing bits on divide-by input lines to divide-by output lines of the same order as said divide-by input line bit position, or transferring said divide-by input line bits to respective ones of said divide-by output lines which are more than one bit position lower in order than divide-by input line bit positions. A weighting function circuit comprises two such matrices which commonly receive the input word for shifting it in different ways, and a combining circuit for combining the shifted words produced by the matrices to produce a weighted word (Fig. 2 not shown). A digital filter comprises the weighting function circuit allowing reduced complexity and higher speed in coefficient multiplication.

公开(公告)号：AU5983186A

公开(公告)日：1987-01-22

申请号：AU5983186

申请日：1986-07-08

Applicant: RCA CORP

Inventor： CHRISTOPHER LAUREN ANN

IPC: H03M1/66 ,  G06F7/38 ,  G06F7/48 ,  G06F7/508 ,  G06F7/544 ,  H03K19/094 ,  H03K19/21 ,  H03M7/00

Abstract: Circuitry for forming the twos complement or ones complement of N-bit binary numbers is described. The circuitry includes N stages each of which contains an exclusive NOR gate (300, 310, 320, 330, 340, 350). A first input terminal (B) of the exclusive NOR gate is coupled to receive one bit of the input value and a second input terminal (C) is coupled to receive the carry output signal from the previous stage. A logic one or logic zero is applied to the second input terminal (C) of the exclusive NOR gate (300) of the stage which processes the least significant bit of the binary word if the circuitry is to provide a twos complement or ones complement value respectively. The carry output signal for each stage is generated by ANDing (302, 312, 322, 334, 342) a logically inverted version of the input bit signal with the carry input signal applied to the stage. An application of the complementing circuitry in an absolute value circuit is also described. In this application, the carry input signal to each stage is ORed (612, 622, 632, 642, 652) with a logically inverted version of the sign bit of the input value and the result is applied to the second input terminal (C) of the exclusive NOR gate. This circuitry complements only negative values, passing positive values unchanged.

公开(公告)号：FI862883A0

公开(公告)日：1986-07-08

申请号：FI862883

申请日：1986-07-08

Applicant: RCA CORP

Inventor： CHRISTOPHER LAUREN ANN

IPC: G06F7/38 ,  H03M1/66 ,  G06F7/48 ,  G06F7/508 ,  G06F7/544 ,  H03K19/094 ,  H03K19/21 ,  H03M7/00 ,  G06F

Abstract: Circuitry for forming the twos complement or ones complement of N-bit binary numbers is described. The circuitry includes N stages each of which contains an exclusive NOR gate (300, 310, 320, 330, 340, 350). A first input terminal (B) of the exclusive NOR gate is coupled to receive one bit of the input value and a second input terminal (C) is coupled to receive the carry output signal from the previous stage. A logic one or logic zero is applied to the second input terminal (C) of the exclusive NOR gate (300) of the stage which processes the least significant bit of the binary word if the circuitry is to provide a twos complement or ones complement value respectively. The carry output signal for each stage is generated by ANDing (302, 312, 322, 334, 342) a logically inverted version of the input bit signal with the carry input signal applied to the stage. An application of the complementing circuitry in an absolute value circuit is also described. In this application, the carry input signal to each stage is ORed (612, 622, 632, 642, 652) with a logically inverted version of the sign bit of the input value and the result is applied to the second input terminal (C) of the exclusive NOR gate. This circuitry complements only negative values, passing positive values unchanged.

公开(公告)号：FR2499289A1

公开(公告)日：1982-08-06

申请号：FR8201193

申请日：1982-01-26

Applicant: RCA CORP

Inventor： CHRISTOPHER LAUREN ANN ,  REITMEIER GLENN ARTHUR ,  SMITH TERRENCE RAYMOND ,  STROLLE CHRISTOPHER HUGH

IPC: G06F1/02 ,  G06F1/03 ,  G06F7/548 ,  G06F12/02 ,  G06F17/17 ,  G06G7/26 ,  G09G5/39 ,  G11C7/00 ,  G11C8/04 ,  G11C8/12 ,  G11C8/16 ,  H03H17/02 ,  H03H17/06 ,  H04N9/78 ,  G11C8/02

公开(公告)号：DE3202365A1

公开(公告)日：1982-08-05

申请号：DE3202365

申请日：1982-01-26

Applicant: RCA CORP

Inventor： CHRISTOPHER LAUREN ANN ,  REITMEIER GLENN ARTHUR ,  SMITH TERRENCE RAYMOND ,  CHRISTOPHER HUGH STROLLE

IPC: G06F1/02 ,  G06F1/03 ,  G06F7/548 ,  G06F12/02 ,  G06F17/17 ,  G06G7/26 ,  G09G5/39 ,  G11C7/00 ,  G11C8/04 ,  G11C8/12 ,  G11C8/16 ,  H03H17/02 ,  H03H17/06 ,  H04N9/78 ,  G11C8/00 ,  G06F3/14 ,  G09G1/02

公开(公告)号：FI862883A

公开(公告)日：1987-01-16

申请号：FI862883

申请日：1986-07-08

Applicant: RCA CORP

Inventor： CHRISTOPHER LAUREN ANN

IPC: G06F7/38 ,  H03M1/66 ,  G06F7/48 ,  G06F7/508 ,  G06F7/544 ,  H03K19/094 ,  H03K19/21 ,  H03M7/00 ,  G06F

Abstract: Circuitry for forming the twos complement or ones complement of N-bit binary numbers is described. The circuitry includes N stages each of which contains an exclusive NOR gate (300, 310, 320, 330, 340, 350). A first input terminal (B) of the exclusive NOR gate is coupled to receive one bit of the input value and a second input terminal (C) is coupled to receive the carry output signal from the previous stage. A logic one or logic zero is applied to the second input terminal (C) of the exclusive NOR gate (300) of the stage which processes the least significant bit of the binary word if the circuitry is to provide a twos complement or ones complement value respectively. The carry output signal for each stage is generated by ANDing (302, 312, 322, 334, 342) a logically inverted version of the input bit signal with the carry input signal applied to the stage. An application of the complementing circuitry in an absolute value circuit is also described. In this application, the carry input signal to each stage is ORed (612, 622, 632, 642, 652) with a logically inverted version of the sign bit of the input value and the result is applied to the second input terminal (C) of the exclusive NOR gate. This circuitry complements only negative values, passing positive values unchanged.

公开(公告)号：IT1151701B

公开(公告)日：1986-12-24

申请号：IT1928382

申请日：1982-01-25

Applicant: RCA CORP

Inventor： CHRISTOPHER LAUREN ANN ,  REITMEIER GLENN ARTHUR ,  SMITH TERRENCE RAYMOND ,  STROLLE CHRISTOPHER HUGH

IPC: G06F1/02 ,  G06F1/03 ,  G06F7/548 ,  G06F12/02 ,  G06F17/17 ,  G06G7/26 ,  G09G5/39 ,  G11C7/00 ,  G11C8/04 ,  G11C8/12 ,  G11C8/16 ,  H03H17/02 ,  H03H17/06 ,  H04N9/78 ,  G11C

公开(公告)号：FR2511562A1

公开(公告)日：1983-02-18

申请号：FR8214133

申请日：1982-08-13

Applicant: RCA CORP

Inventor： CHRISTOPHER LAUREN ANN ,  STECKLER STEVEN ALAN

IPC: H03H17/06 ,  H03H17/02

Abstract: The invention creates a digital FIR (finite impulse response) filter in which weight function circuits (20, 22, 24, 26) are utilised several times and supply weighted signals at a plurality of different delay points (32, 42, 52, 46, 36, 66) of the shift register. In a preferred embodiment of the invention, the FIR filter contains a number of modules (60) which in each case contain a weight function circuit (22) and several adders (32, 36) and delay elements (30, 34), which are connected together in such a manner that a filter with "convoluted" structure is obtained.