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    Controllable shift matrix weighting function circuits and digital circuits especially filters using such a matrix
    2.
    发明专利
    Controllable shift matrix weighting function circuits and digital circuits especially filters using such a matrix 未知

    公开(公告)号：GB2104695A

    公开(公告)日：1983-03-09

    申请号：GB8222991

    申请日：1982-08-10

    Applicant: RCA CORP

    Inventor： CHRISTOPHER LAUREN ANN

    IPC: H03H17/06 ,  G06F7/00

    Abstract: A controllable shift matrix has inputs and outputs and is responsive to bits of an input signal word X(n) at the inputs of ascending order from a least significant bit position to a most significant bit position for controllably producing an output (weighted X(n) the outputs in which the input signal bits may occupy respectively different bit positions. The matrix comprises a plurality of sections (80-88) including at least one divide-by section (82) coupled between the inputs and outputs and including controlled switch means responsive to control signals (C1 ,C1) for selectively passing bits on divide-by input lines to divide-by output lines of the same order as said divide-by input line bit position, or transferring said divide-by input line bits to respective ones of said divide-by output lines which are more than one bit position lower in order than divide-by input line bit positions. A weighting function circuit comprises two such matrices which commonly receive the input word for shifting it in different ways, and a combining circuit for combining the shifted words produced by the matrices to produce a weighted word (Fig. 2 not shown). A digital filter comprises the weighting function circuit allowing reduced complexity and higher speed in coefficient multiplication.

    4.
    发明专利
    未知

    公开(公告)号：FR2511561A1

    公开(公告)日：1983-02-18

    申请号：FR8214134

    申请日：1982-08-13

    Applicant: RCA CORP

    Inventor： CHRISTOPHER LAUREN ANN

    IPC: H03H17/06 ,  H03H17/00

    Abstract: A controllable shift matrix has inputs and outputs and is responsive to bits of an input signal word X(n) at the inputs of ascending order from a least significant bit position to a most significant bit position for controllably producing an output (weighted X(n) the outputs in which the input signal bits may occupy respectively different bit positions. The matrix comprises a plurality of sections (80-88) including at least one divide-by section (82) coupled between the inputs and outputs and including controlled switch means responsive to control signals (C1 ,C1) for selectively passing bits on divide-by input lines to divide-by output lines of the same order as said divide-by input line bit position, or transferring said divide-by input line bits to respective ones of said divide-by output lines which are more than one bit position lower in order than divide-by input line bit positions. A weighting function circuit comprises two such matrices which commonly receive the input word for shifting it in different ways, and a combining circuit for combining the shifted words produced by the matrices to produce a weighted word (Fig. 2 not shown). A digital filter comprises the weighting function circuit allowing reduced complexity and higher speed in coefficient multiplication.

    PERFECCIONAMIENTOS INTRODUCIDOS EN UN APARATO DE N ETAPAS PARA DESARROLLAR EL COMPLEMENTO ARITMETICO DE VALORES BINARIOS DE N BITS.
    8.
    发明专利
    PERFECCIONAMIENTOS INTRODUCIDOS EN UN APARATO DE N ETAPAS PARA DESARROLLAR EL COMPLEMENTO ARITMETICO DE VALORES BINARIOS DE N BITS. 未知

    公开(公告)号：ES2000270A6

    公开(公告)日：1988-02-01

    申请号：ES8600198

    申请日：1986-07-09

    Applicant: RCA CORP

    Inventor： CHRISTOPHER LAUREN ANN

    IPC: H03M1/66 ,  G06F7/38 ,  G06F7/48 ,  G06F7/508 ,  G06F7/544 ,  H03K19/094 ,  H03K19/21 ,  H03M7/00

    Abstract: SE DESCRIBE UN APARATO QUE COMPRENDE UNA DISPOSICION DE CIRCUITO PARA FORMAR EL COMPLEMENTO A DOSES O EL COMPLEMENTO A UNOS DE NUMEROS BINARIOS DE N BITIOS. LA DISPOSICION DE CIRCUITO INCLUYE N ETAPAS, CADA UNA DE LAS CUALES CONTIENE UNA PUERTA NOR (NO-O) EXCLUSIVA. UN PRIMER TERMINAL DE ENTRADA DE LA PUERTA NOR EXCLUSIVA ESTA ACOPLADO PARA RECIBIR UN BITIO DEL VALOR DE ENTRADA Y UN SEGUNDO TERMINAL DE ENTRADA ESTA ACOPLADO PARA RECIBIR LA SEÑAL DE SALIDA PORTADORA DE LA ETAPA ANTERIOR. SE APLICA EN UNO LOGICO O UN CERO LOGICO AL SEGUNDO TERMINAL DE ENTRADA DE LA ETAPA QUE PROCESA EL BITIO MENOS SIGNIFICATIVO DE LA PALABRA BINARIA SI LA DISPOSICION DE CIRCUITO ES PARA PROPORCIONAR UN VALOR DE COMPLEMENTO A DOSES O DE COMPLEMENTO A UNOS, RESPECTIVAMENTE. TAMBIEN SE DESCRIBE LA APLICACION DE LA DISPOSICION DE CIRCUITO EN UN CIRCUITO DE VALORES ABSOLUTOS, COMPLEMENTANDOSE SOLO LOS VALORES NEGATIVOS Y QUEDANDO SIN MODIFICAR LOS VALORES POSITIVOS.

    Digital finite impulse response filter
    9.
    发明专利
    Digital finite impulse response filter 未知

    公开(公告)号：GB2104332A

    公开(公告)日：1983-03-02

    申请号：GB8222992

    申请日：1982-08-10

    Applicant: RCA CORP

    Inventor： STECKLER STEVEN ALAN ,  CHRISTOPHER LAUREN ANN

    IPC: H03H17/06

    Abstract: The filter comprises weighting function circuits (20,22,24,26) which provide weighted signals to pairs of different delay points (32, 36; 42, 46; 52, (56); (62) 30, 66) of the shift register, ie an arrangement for providing symmetrical weightings about a centre point, resulting in a linear phase characteristic. The filter comprises a number of modules (60), each including a weighting function circuit (22) and a pair of adders (32,36) and delay elements (30,34) which are interconnected to give the filter a "folded" structural characteristic.

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