公开(公告)号：US20240422964A1

公开(公告)日：2024-12-19

申请号：US18421187

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Wonsok LEE ,  Juho LEE ,  Daewon HA

IPC: H10B12/00 ,  H01L29/10

Abstract: A semiconductor memory device includes a memory cell array having a three-dimensional structure, the memory cell array including a plurality of memory cells repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction, wherein the first lateral direction and the second lateral direction are perpendicular to each other, and the vertical direction is perpendicular to each of the first lateral direction and the second lateral direction, wherein each of the plurality of memory cells includes two transistors including at a least portions of two word lines passing through the memory cell in the vertical direction and at least portions of two bit lines respectively on both sides of the two word lines in the first lateral direction, each of the two bit line extending along the second lateral direction, and each of the plurality of memory cells does not include a capacitor.

公开(公告)号：US20230055147A1

公开(公告)日：2023-02-23

申请号：US17741701

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Wonsok LEE ,  Min Hee CHO

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, a channel pattern between the bit line and the word line, the channel pattern including a horizontal channel portion, which is connected to the bit line, and a vertical channel portion, which is extended from the horizontal channel portion in a third direction perpendicular to the first and second directions, and a gate insulating pattern between the word line and the channel pattern. The horizontal channel portion of the channel pattern may be disposed parallel to a fourth direction that is inclined to the first and second directions.

公开(公告)号：US20230009575A1

公开(公告)日：2023-01-12

申请号：US17690371

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee CHO ,  Mintae RYU ,  Sungwon YOO ,  Wonsok LEE ,  Hyunmog PARK ,  Kiseok LEE

IPC: H01L29/786

Abstract: A semiconductor device including a conductive line on a substrate, a first gate electrode on the conductive line, a second gate electrode separated by a gate isolation insulating layer on the first gate electrode, a first channel layer on a side surface of the first gate electrode, with a first gate insulating layer therebetween, a first source/drain region on another side surface of the first gate electrode, a second channel layer on another side surface of the second gate electrode on a side that is opposite to the first channel layer, with a second gate insulating layer therebetween, a second source/drain region on the second channel layer, and a third source/drain region on the first channel layer and on a side surface of the second gate electrode on a same side as the first channel layer may be provided.

公开(公告)号：US20220302198A1

公开(公告)日：2022-09-22

申请号：US17528237

申请日：2021-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongsoon KANG ,  Mintae RYU ,  Minsu LEE ,  Wonsok LEE

IPC: H01L27/146 ,  H01L27/148

Abstract: An image sensor includes a first substrate. A photoelectric conversion region is in the first substrate. A first interlayer insulating layer is on the first substrate. A transistor includes a bonding insulating layer on the first interlayer insulating layer, a semiconductor layer on the bonding insulating layer, and a first gate on the semiconductor layer. A bias pad is spaced apart from the semiconductor layer by the bonding insulating layer. The bias pad overlaps the first gate in a planar view. A second interlayer insulating layer covers the transistor.

公开(公告)号：US20220149092A1

公开(公告)日：2022-05-12

申请号：US17376333

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongsoon KANG ,  Buil JUNG ,  Hyunmog PARK ,  Wonsok LEE

IPC: H01L27/146

Abstract: An image sensor includes a substrate having a pixel area in which a plurality of active areas is defined. A first transistor includes a first gate electrode including a buried gate portion. The buried gate portion is buried in the substrate in a first active area selected from the plurality of active areas. A second transistor includes a second gate electrode overlapping the buried gate portion on the first active area in a vertical direction.