公开(公告)号：DE68922641D1

公开(公告)日：1995-06-22

申请号：DE68922641

申请日：1989-02-13

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： RIVA CARLO

IPC: H01L21/8247 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82

公开(公告)号：DE69018893D1

公开(公告)日：1995-06-01

申请号：DE69018893

申请日：1990-07-09

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： RIVA CARLO

IPC: G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/04 ,  G06F11/20

Abstract: The EEPROM memory cell with 100% redundancy includes two tunnel storage elements (10, 18; 26, 30) which are connected in parallel between a common source voltage (16) and an enabling transistor (22) which is controlled by a transfer terminal (24) and leads to a bit line (14), with respective sensing transistors (12, 28) arranged in series with respect to the storage elements. According to the invention, the cell furthermore includes an auxiliary enabling transistor (40) which is arranged in series on the source and is controlled by the transfer terminal.

公开(公告)号：IT1252025B

公开(公告)日：1995-05-27

申请号：ITMI913196

申请日：1991-11-29

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： GHEZZI PAOLO ,  RIVA CARLO

IPC: G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C

公开(公告)号：DE3787421D1

公开(公告)日：1993-10-21

申请号：DE3787421

申请日：1987-06-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： MAGGIONI FRANCO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82

公开(公告)号：DE3780784D1

公开(公告)日：1992-09-03

申请号：DE3780784

申请日：1987-12-02

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  CORDA GIUSEPPE ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  G11C17/00

公开(公告)号：DE3780767D1

公开(公告)日：1992-09-03

申请号：DE3780767

申请日：1987-10-23

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： RIVA CARLO

IPC: H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L27/10

公开(公告)号：IT1232354B

公开(公告)日：1992-01-28

申请号：IT2161989

申请日：1989-09-04

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： GHEZZI PAOLO ,  RIVA CARLO ,  VALENTINI GRAZIA

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C

Abstract: The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor (20), sensing transistor (22) having a floating gate (5), control gate (10) with a capacitive coupling to the floating gate (5) and a tunnel area (23) with thin oxide (9), comprises a first step (29) involving the definition of active areas (41, 42) free of field oxide (11), a second step (30) involving an ionic implantation (10 min ) at a coupling area (24) between the control gate (10) and the floating gate (5), a third step (31) involving the creation of gate oxide (21) at the active areas (41, 42), a fourth step (32) involving an additional ionic implantation (10 sec , 8) at said coupling area (24) between the control gate (10) and the floating gate (5) and at said tunnel area (23), a fifth step (33) involving the removal of the gate oxide (21) superimposed over said areas (24, 23), a sixth step (34) involving the differentiated growth of coupling oxide (12) and tunnel oxide (9) at said coupling areas (24) and tunnel areas (23) and a seventh step (35) involving the deposition of a layer of polysilicon (5) constituting the floating gate.

公开(公告)号：IT8921402D0

公开(公告)日：1989-08-01

申请号：IT2140289

申请日：1989-08-01

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： RIVA CARLO

IPC: G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/115

Abstract: The EEPROM memory cell with 100% redundancy includes two tunnel storage elements (10, 18; 26, 30) which are connected in parallel between a common source voltage (16) and an enabling transistor (22) which is controlled by a transfer terminal (24) and leads to a bit line (14), with respective sensing transistors (12, 28) arranged in series with respect to the storage elements. According to the invention, the cell furthermore includes an auxiliary enabling transistor (40) which is arranged in series on the source and is controlled by the transfer terminal.

公开(公告)号：DE69221090T2

公开(公告)日：1998-03-05

申请号：DE69221090

申请日：1992-11-17

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： GHEZZI PAOLO ,  PIO FEDERICO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A method for forming thin oxide portions in electrically erasable and programmable read-only memory cells, including the use of the enhanced oxidation effect and the lateral diffusion of heavy doping, for obtaining a tunnel portion whose dimensions are smaller than the resolution of the photolithographic method used.

公开(公告)号：DE69018893T2

公开(公告)日：1995-12-21

申请号：DE69018893

申请日：1990-07-09

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： RIVA CARLO

IPC: G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/04 ,  G06F11/20

Abstract: The EEPROM memory cell with 100% redundancy includes two tunnel storage elements (10, 18; 26, 30) which are connected in parallel between a common source voltage (16) and an enabling transistor (22) which is controlled by a transfer terminal (24) and leads to a bit line (14), with respective sensing transistors (12, 28) arranged in series with respect to the storage elements. According to the invention, the cell furthermore includes an auxiliary enabling transistor (40) which is arranged in series on the source and is controlled by the transfer terminal.