公开(公告)号：DE69030544T2

公开(公告)日：1997-08-21

申请号：DE69030544

申请日：1990-08-28

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： GHEZZI PAOLO ,  RIVA CARLO ,  VALENTINI GRAZIA

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

Abstract: The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor (20), sensing transistor (22) having a floating gate (5), control gate (10) with a capacitive coupling to the floating gate (5) and a tunnel area (23) with thin oxide (9), comprises a first step (29) involving the definition of active areas (41, 42) free of field oxide (11), a second step (30) involving an ionic implantation (10 min ) at a coupling area (24) between the control gate (10) and the floating gate (5), a third step (31) involving the creation of gate oxide (21) at the active areas (41, 42), a fourth step (32) involving an additional ionic implantation (10 sec , 8) at said coupling area (24) between the control gate (10) and the floating gate (5) and at said tunnel area (23), a fifth step (33) involving the removal of the gate oxide (21) superimposed over said areas (24, 23), a sixth step (34) involving the differentiated growth of coupling oxide (12) and tunnel oxide (9) at said coupling areas (24) and tunnel areas (23) and a seventh step (35) involving the deposition of a layer of polysilicon (5) constituting the floating gate.

公开(公告)号：IT8921619D0

公开(公告)日：1989-09-04

申请号：IT2161989

申请日：1989-09-04

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： GHEZZI PAOLO ,  RIVA CARLO ,  VALENTINI GRAZIA

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor (20), sensing transistor (22) having a floating gate (5), control gate (10) with a capacitive coupling to the floating gate (5) and a tunnel area (23) with thin oxide (9), comprises a first step (29) involving the definition of active areas (41, 42) free of field oxide (11), a second step (30) involving an ionic implantation (10 min ) at a coupling area (24) between the control gate (10) and the floating gate (5), a third step (31) involving the creation of gate oxide (21) at the active areas (41, 42), a fourth step (32) involving an additional ionic implantation (10 sec , 8) at said coupling area (24) between the control gate (10) and the floating gate (5) and at said tunnel area (23), a fifth step (33) involving the removal of the gate oxide (21) superimposed over said areas (24, 23), a sixth step (34) involving the differentiated growth of coupling oxide (12) and tunnel oxide (9) at said coupling areas (24) and tunnel areas (23) and a seventh step (35) involving the deposition of a layer of polysilicon (5) constituting the floating gate.

公开(公告)号：DE69030544D1

公开(公告)日：1997-05-28

申请号：DE69030544

申请日：1990-08-28

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： GHEZZI PAOLO ,  RIVA CARLO ,  VALENTINI GRAZIA

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

Abstract: The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor (20), sensing transistor (22) having a floating gate (5), control gate (10) with a capacitive coupling to the floating gate (5) and a tunnel area (23) with thin oxide (9), comprises a first step (29) involving the definition of active areas (41, 42) free of field oxide (11), a second step (30) involving an ionic implantation (10 min ) at a coupling area (24) between the control gate (10) and the floating gate (5), a third step (31) involving the creation of gate oxide (21) at the active areas (41, 42), a fourth step (32) involving an additional ionic implantation (10 sec , 8) at said coupling area (24) between the control gate (10) and the floating gate (5) and at said tunnel area (23), a fifth step (33) involving the removal of the gate oxide (21) superimposed over said areas (24, 23), a sixth step (34) involving the differentiated growth of coupling oxide (12) and tunnel oxide (9) at said coupling areas (24) and tunnel areas (23) and a seventh step (35) involving the deposition of a layer of polysilicon (5) constituting the floating gate.

公开(公告)号：IT1232354B

公开(公告)日：1992-01-28

申请号：IT2161989

申请日：1989-09-04

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： GHEZZI PAOLO ,  RIVA CARLO ,  VALENTINI GRAZIA

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C

Abstract: The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor (20), sensing transistor (22) having a floating gate (5), control gate (10) with a capacitive coupling to the floating gate (5) and a tunnel area (23) with thin oxide (9), comprises a first step (29) involving the definition of active areas (41, 42) free of field oxide (11), a second step (30) involving an ionic implantation (10 min ) at a coupling area (24) between the control gate (10) and the floating gate (5), a third step (31) involving the creation of gate oxide (21) at the active areas (41, 42), a fourth step (32) involving an additional ionic implantation (10 sec , 8) at said coupling area (24) between the control gate (10) and the floating gate (5) and at said tunnel area (23), a fifth step (33) involving the removal of the gate oxide (21) superimposed over said areas (24, 23), a sixth step (34) involving the differentiated growth of coupling oxide (12) and tunnel oxide (9) at said coupling areas (24) and tunnel areas (23) and a seventh step (35) involving the deposition of a layer of polysilicon (5) constituting the floating gate.