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公开(公告)号:AU2118799A
公开(公告)日:1999-03-01
申请号:AU2118799
申请日:1998-08-11
Applicant: SONY CORP
Inventor: IKEDA YASUNARI , IKEDA TAMOTSU
IPC: H03M13/35 , H04J3/06 , H04N19/33 , H04N19/423 , H04N19/60 , H04N19/65 , H04N19/70 , H04N19/88 , H04N19/89 , H04N21/438
Abstract: Frame synchronizing signals held by a synchronization register 2 are Reed-Solomon-coded by a Reed-Solomon coding circuit 4, then interleaved by an interleave circuit 5, then convolutional-coded by a convolutional coding circuit 10, then mapped by a mapping circuit 11, and then outputted. Thus, the frame synchronizing signals can be stably and quickly detected.
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12.
公开(公告)号:GB2110900B
公开(公告)日:1985-06-19
申请号:GB8233398
申请日:1982-11-23
Applicant: SONY CORP
Inventor: OKADA TAKASHI , IKEDA YASUNARI , TANAKA YUTAKA
Abstract: A double-scanning non-interlace television receiver with a vertical aperture correction circuit for receiving an interlace television signal having alternating odd and even fields of scanned lines which are interlaced, as displayed, comprises a receiver circuit which receives the interlace television signal and which generates interlace scanning line signals for each of the fields, a visual display apparatus, a non-interlace converting circuit which converts the interlace scanning line signals for each of the fields to non-interlace scanning line signals which are displayed on the visual display apparatus, with each of the scanned lines being scanned twice, and a high frequency emphasizing circuit which emphasizes the high frequency components of the interlace scanning line signals.
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公开(公告)号:DE3330570A1
公开(公告)日:1984-03-08
申请号:DE3330570
申请日:1983-08-24
Applicant: SONY CORP
Inventor: TANAKA YUTAKA , IKEDA YASUNARI , NAKANO HIROSHI
Abstract: A television receiver having a signal input terminal supplied with an interlace video signal and a signal coverter connected to the input terminal for converting the interlace video signal to a non-interlace signal to be displayed. The signal converter includes a signal inserting circuit for inserting new line signals between two successive line signals of the interlace signal, the new line signals being formed by interpolating one of the preceding and succeeding line signals in the interlace signal. A three dimensional filter is connected to the signal converter for attentuating vertical and horizontal high frequency components in the non-interlace video signal only when the non-interlace signal includes both of the vertical and horizontal high frequency components.
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公开(公告)号:BR0101473B1
公开(公告)日:2014-07-22
申请号:BR0101473
申请日:2001-04-12
Applicant: SONY CORP
Inventor: OKADA TAKAHIRO , MIYATO YOSHIKAZU , IKEDA YASUNARI , IKEDA TAMOTSU
Abstract: The time required for switch the channel can be remarkably curtailed. When broadcasting signals through a plurality of information channels with an OFDM system, the plurality of information channels are multiplexed in the sense of frequency and collectively subjected to IFFT modulation for connected transmission instead of subjecting the plurality of information channels independently to OFDM modulation for transmission. With this arrangement, the efficiency of exploitation of frequencies is improved. According to the invention, the OFDM frames are synchronized for each information channel for the purpose of connected transmission. Then, the OFDM receiver can switch the information channel for signal reception, maintaining the frame synchronizing signals.
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公开(公告)号:BR0008667B1
公开(公告)日:2014-04-15
申请号:BR0008667
申请日:2000-03-06
Applicant: SONY CORP
Inventor: OKADA TAKAHIRO , IKEDA YASUNARI
IPC: H04J11/00 , H04B1/04 , H04J20060101 , H04L5/06
Abstract: A transmission apparatus which prevents adversely affects from an adjacent channel even without provision of a guard band. An information sequence 1 input to a mapping unit 21 - 1 of the transmission apparatus is mapped onto predetermined signal points by QAM modulation, etc. and output to a frequency converter 22 - 1 . The frequency converter 22 - 1 converts the frequency according to a center frequency of an input signal and outputs the result to a multiplexer 23 . The other data series are processed in the same way as the data series 1 are output to the multiplexer 23 . The multiplexer 23 multiplexes a plurality of input signals, while an IFFT processor 24 performs an inverse Fourier transform on the multiplexed signals all at once. The inverse Fourier transformed signal is quadrature-modulated by a quadrature modulator 26 , converted to the RF band signal by the frequency converter 28 , and transmitted from an antenna 30.
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公开(公告)号:DE60143236D1
公开(公告)日:2010-11-25
申请号:DE60143236
申请日:2001-04-05
Applicant: SONY CORP
Inventor: OKADA TAKAHIRO , HYAKUDAI TOSHIHISA , MATSUMIYA ISAO , IKEDA YASUNARI
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公开(公告)号:ES2264186T3
公开(公告)日:2006-12-16
申请号:ES98303415
申请日:1998-04-30
Applicant: SONY CORP
Inventor: HYAKUDAI TOSHIHISA , OKADA TAKAHIRO , IKEDA YASUNARI
Abstract: LA INVENCION SE REFIERE A UNA TECNICA PARA RECIBIR UNA SEÑAL OFDM QUE ESTA DISPUESTA PARA REPRODUCIR DE FORMA PRECISA UNA SEÑAL DE RELOJ. LOS DATOS DEL CANAL I Y LOS DATOS DEL CANAL Q SE DEMODULAN DE FORMA DIFERENCIAL MEDIANTE UN CIRCUITO DEMODULADOR DIFERENCIAL (503) Y SE SUMINISTRAN A UNA ROM (512). LA ROM (512) LEE UNA CANTIDAD DE CAMBIO DE FASE INTERSIMBOLICA, CORRESPONDIENTE A LOS DATOS DEMODULADOS DE FORMA DIFERENCIAL, SUMINISTRANDO LOS MISMOS A UN CIRCUITO DE PUERTA (514) QUE EXTRAE SOLO UN COMPONENTE CORRESPONDIENTE A CADA UNA DE LAS SEÑALES PILOTO DE LOS DATOS DE ENTRADA, SUMINISTRANDO EL COMPONENTE EXTRAIDO A UN CIRCUITO INVERSOR DE SIGNO (521) Y A UN SELECTOR (522). EL SELECTOR (522) SELECCIONA LA SALIDA DEL CIRCUITO DE PUERTA (514) SI LA SEÑAL PILOTO ES UN VALOR DE FRECUENCIA POSITIVA, O SELECCIONA LA SALIDA DEL CIRCUITO INVERSOR DE SIGNO (521) SI LA SEÑAL PILOTO ES UN VALOR DE FRECUENCIA NEGATIVA, SUMINISTRANDO EL VALOR OBTENIDO A UN CIRCUITO DE SUMAS ACUMULATIVAS (515). EL CIRCUITO DE SUMAS ACUMULATIVAS (515) REALIZA UNA SUMA ACUMULATIVA DE LA SALIDA DE LOS VALORES DEL SELECTOR (522) A TRAVES DE UN PERIODO DE SIMBOLO, LLEVANDO EL RESULTADO DE LA SUMA A UN CIRCUITO DE PROMEDIO (516). EL CIRCUITO DE PROMEDIO (516) PROMEDIA LA SALIDA DEL CIRCUITO DE SUMA ACUMULATIVA (515) Y CONTROLA LA FRECUENCIA DE OSCILACION DE UNA SEÑAL DE RELOJ, DE ACUERDO CON EL VALOR OBTENIDO POR EL CIRCUITO DE PROMEDIO (516).
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19.
公开(公告)号:AU2005203632A1
公开(公告)日:2005-09-01
申请号:AU2005203632
申请日:2005-08-15
Applicant: SONY CORP
Inventor: IKEDA YASUNARI , KOZAKI YASUNARI
IPC: G06F17/14
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公开(公告)号:HK1048401A1
公开(公告)日:2003-03-28
申请号:HK02107467
申请日:2002-10-15
Applicant: NIPPO HOSO KYOKAI , SONY CORP
Inventor: IKEDA YASUNARI , HYAKUDAI TOSHIHISA , OKADA TAKAHIRO , IKEDA TAMOTSU , KURODA TORU , IAI NAOHIKO , TSUCHIDA KENICHI , SASAKI MAKOTO
Abstract: A frequency interleaving circuit frequency-interleaves main signals generated according to sound data by parameters set according to frequencies of transmission channels. A sub-signal generating circuit generates sub-signals for transmission control including pilot signals. Mapping circuits modulate the sub-signals by using pseudo-random sequences generated based on initial values of random codes set according to frequencies of transmission channels. The frequency-interleaved main signals and the sub-signals modulated by the mapping circuits are OFDM-modulated. Then, they are converted to the frequencies of the transmission channels. An increase of a dynamic range of transmission signals can be suppressed by controlling the initial values of random codes set.
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