公开(公告)号：ITVA20020020D0

公开(公告)日：2002-03-04

申请号：ITVA20020020

申请日：2002-03-04

Applicant: ST MICROELECTRONICS SRL

Inventor： CASTALDO ENRICO ,  CONTE ANTONINO

IPC: H02M3/07

Abstract: A circuit for regulating an output voltage of a charge pump includes a regulator connected to an output of the charge pump. The regulator includes a voltage divider for dividing the output voltage. A filter has a first input for receiving the divided output voltage, a second input for receiving a control signal, and an output for providing a filtered divided output voltage. A comparator has a first input for receiving the divided output voltage, a second input for receiving a reference voltage, a third input for receiving the filtered divided output voltage, and an output for providing a digital signal based upon a comparison of the divided output signal, the reference voltage and the filtered divided output voltage. A logic control circuit has a first input for receiving a clock signal, a second input for receiving the digital signal from the comparator, and an output for providing a timing signal. A phase generator circuit has an input for receiving the timing signal from the logic control circuit for generating control phases for the charge pump.

公开(公告)号：DE602005010403D1

公开(公告)日：2008-11-27

申请号：DE602005010403

申请日：2005-05-25

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  SBERNO GIAMPIERO ,  MICCICHE MARIO ,  CASTALDO ENRICO

IPC: G11C16/16

Abstract: A non-volatile memory device is proposed. The memory device (100) includes a plurality of blocks (115) of memory cells (125), each block having a common biasing node (SL) for all the memory cells of the block, biasing means (150) for providing a biasing voltage, and selection means (140, 145) for selectively applying the biasing voltage to the biasing node of a selected block, for each block the selection means including first switching means (N8, N9, N10) and second switching means (N7) connected in series, the first switching means being connected with the biasing node and the second switching means being connected with the biasing means, wherein the second switching means of all the blocks are connected in parallel, the selection means including means (145) for closing the first switching means of the selected block and the second switching means of all the blocks, and for opening the second switching means of each unselected block.