公开(公告)号：DE602005010403D1

公开(公告)日：2008-11-27

申请号：DE602005010403

申请日：2005-05-25

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  SBERNO GIAMPIERO ,  MICCICHE MARIO ,  CASTALDO ENRICO

IPC: G11C16/16

Abstract: A non-volatile memory device is proposed. The memory device (100) includes a plurality of blocks (115) of memory cells (125), each block having a common biasing node (SL) for all the memory cells of the block, biasing means (150) for providing a biasing voltage, and selection means (140, 145) for selectively applying the biasing voltage to the biasing node of a selected block, for each block the selection means including first switching means (N8, N9, N10) and second switching means (N7) connected in series, the first switching means being connected with the biasing node and the second switching means being connected with the biasing means, wherein the second switching means of all the blocks are connected in parallel, the selection means including means (145) for closing the first switching means of the selected block and the second switching means of all the blocks, and for opening the second switching means of each unselected block.

公开(公告)号：FR2908919B1

公开(公告)日：2014-03-07

申请号：FR0759104

申请日：2007-11-16

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONIO ,  MICCICHE MARIO ,  LO GIUDICE GIANBATTISTA ,  DI MARTINO ALBERTO ,  SBERNO GIAMPIERO

IPC: G11C16/16 ,  G05F3/24

公开(公告)号：ITMI20020793A1

公开(公告)日：2003-10-15

申请号：ITMI20020793

申请日：2002-04-15

Applicant: ST MICROELECTRONICS SRL

Inventor： DEMANGE NICOLAS ,  TORRISI SALVATORE ,  SBERNO GIAMPIERO

IPC: G11C7/18 ,  G11C11/22

Abstract: A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local word lines branching off from the word line associated with the at least one row, each local word line being connected to a respective group of memory units of the line. Selective connection means allow to selectively connect one of the local word lines to the respective word line. The arrangement of memory units further includes a plurality of local plate biasing lines, each one associated with the memory units of a respective group of memory units, for selectively driving the memory units of the respective groups.

公开(公告)号：ITMI20011812A1

公开(公告)日：2003-02-24

申请号：ITMI20011812

申请日：2001-08-24

Applicant: ST MICROELECTRONICS SRL

Inventor： DEMANGE NICOLAS ,  TORRISI SALVATORE ,  SBERNO GIAMPIERO

IPC: G11C11/22

Abstract: A method of reading and restoring data stored in a ferroelectric memory cell is disclosed. The cell includes a first transistor and first ferroelectric capacitor connected, in series with each other, between a first bitline and an auxiliary line, a second transistor and second ferroelectric capacitor connected, in series with each other, between a second bitline and the auxiliary line, the first and second transistors having respective control terminals connected to a common wordline. The reading method includes precharging the first and second capacitors, applying a read pulse to the cell such that the state of the first capacitor is changed, reading the cell by a sensing means, and restoring the first capacitor to an initial state. Advantageously, the reading method further includes changing the state of the second capacitor during the step of restoring the first capacitor, and further restoring the second capacitor to an initial state, such that the voltages being applied to the transistors during any of the steps are lower than a voltage reference of the cell. Also disclosed is a method of writing and restoring data stored in a ferroelectric memory cell.

公开(公告)号：ITMI20020793D0

公开(公告)日：2002-04-15

申请号：ITMI20020793

申请日：2002-04-15

Applicant: ST MICROELECTRONICS SRL

Inventor： DEMANGE NICOLAS ,  TORRISI SALVATORE ,  SBERNO GIAMPIERO

IPC: G11C7/18 ,  G11C11/22

Abstract: A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local word lines branching off from the word line associated with the at least one row, each local word line being connected to a respective group of memory units of the line. Selective connection means allow to selectively connect one of the local word lines to the respective word line. The arrangement of memory units further includes a plurality of local plate biasing lines, each one associated with the memory units of a respective group of memory units, for selectively driving the memory units of the respective groups.

公开(公告)号：ITMI20020673D0

公开(公告)日：2002-03-29

申请号：ITMI20020673

申请日：2002-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： DEMANGE NICOLAS ,  TORRISI SALVATORE ,  SBERNO GIAMPIERO

IPC: G11C11/22

Abstract: A method and circuit for accessing a memory location comprising at least one respective ferroelectric storage unit of a matrix of ferroelectric storage units, the memory location is selected by connecting a first terminal of a ferroelectric storage element of the at least one respective storage unit to a respective access line to the memory location; at least another memory location to which is not intended to be accessed is also selected. A second terminal of the ferroelectric storage element is biased to a prescribed access electric potential, and an electric potential on the access line is sensed; the second terminal of the ferroelectric storage elements of the other memory location is also biased to the access potential.

公开(公告)号：ITMI20020673A1

公开(公告)日：2003-09-29

申请号：ITMI20020673

申请日：2002-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： DEMANGE NICOLAS ,  TORRISI SALVATORE ,  SBERNO GIAMPIERO

IPC: G11C11/22

Abstract: A method and circuit for accessing a memory location comprising at least one respective ferroelectric storage unit of a matrix of ferroelectric storage units, the memory location is selected by connecting a first terminal of a ferroelectric storage element of the at least one respective storage unit to a respective access line to the memory location; at least another memory location to which is not intended to be accessed is also selected. A second terminal of the ferroelectric storage element is biased to a prescribed access electric potential, and an electric potential on the access line is sensed; the second terminal of the ferroelectric storage elements of the other memory location is also biased to the access potential.

公开(公告)号：ITMI20011812D0

公开(公告)日：2001-08-24

申请号：ITMI20011812

申请日：2001-08-24

Applicant: ST MICROELECTRONICS SRL

Inventor： DEMANGE NICOLAS ,  TORRISI SALVATORE ,  SBERNO GIAMPIERO

IPC: G11C11/22

Abstract: A method of reading and restoring data stored in a ferroelectric memory cell is disclosed. The cell includes a first transistor and first ferroelectric capacitor connected, in series with each other, between a first bitline and an auxiliary line, a second transistor and second ferroelectric capacitor connected, in series with each other, between a second bitline and the auxiliary line, the first and second transistors having respective control terminals connected to a common wordline. The reading method includes precharging the first and second capacitors, applying a read pulse to the cell such that the state of the first capacitor is changed, reading the cell by a sensing means, and restoring the first capacitor to an initial state. Advantageously, the reading method further includes changing the state of the second capacitor during the step of restoring the first capacitor, and further restoring the second capacitor to an initial state, such that the voltages being applied to the transistors during any of the steps are lower than a voltage reference of the cell. Also disclosed is a method of writing and restoring data stored in a ferroelectric memory cell.