公开(公告)号：DE69517718D1

公开(公告)日：2000-08-10

申请号：DE69517718

申请日：1995-02-15

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: G11C7/00 ,  G06F7/78 ,  H04N5/907 ,  H04N7/26 ,  H04N7/32 ,  G06F7/00

Abstract: The circuit includes a double access memory system (10) connected through busses to systems for writing data in an initial order and for reading the data in a predetermined final order. A control register (14) allows memory read operations only when its content is non-zero. The register has its contents decremented at each read operation and incremented by 1 plus the difference between the rank of the input data and the rank of the output data, or zero if the difference is negative. Output data can be read even if all the input data is not available.

公开(公告)号：DE69422228D1

公开(公告)日：2000-01-27

申请号：DE69422228

申请日：1994-06-27

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: G06F12/04 ,  G06F13/40 ,  H04N7/26 ,  H04N7/36 ,  H04N7/50 ,  H04N7/24

Abstract: The present invention relates to a processor system comprising a data bus with a fixed size of N bits (D64) connected to a memory (12) for words of n bits by a bus with a size of n bits (D16), where N is a multiple of n and where n is variable. The system comprises means (62) for, on each execution by the processor of an instruction for writing an N-bit word into the memory, successively writing each sub-word of n bits constituting this N-bit word to distinct addresses; and means (60, 64, 65, 66) for, on each execution of an instruction for reading an N-bit word from the memory, successively reading from the said memory at distinct addresses sub-words of n bits, and juxtaposing these sub-words on the bus of fixed size.

公开(公告)号：DE69419663T2

公开(公告)日：2000-01-27

申请号：DE69419663

申请日：1994-05-20

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

Abstract: The present invention relates to a processor architecture for executing a current task from a plurality of possible tasks. The architecture comprises: a plurality of instruction pointers (IP) associated respectively with the possible tasks and each containing the address of the current instruction to be executed of the associated task, one only of these pointers being capable of being enabled at a time in order to supply its contents as address to the memory; a priority level decoder (18) assigning a predetermined priority level to each enquiry signal and enabling the instruction pointer associated with the active enquiry signal of highest priority level; and means (20) for incrementing the contents of the enabled instruction pointer and for reinitialising it at the start address of the associated program when its contents reach the finish address of the associated program.

公开(公告)号：DE69706367D1

公开(公告)日：2001-10-04

申请号：DE69706367

申请日：1997-05-28

Applicant: ST MICROELECTRONICS SA

Inventor： DOUCHE JEAN-LOUIS ,  ARTIERI ALAIN ,  IMBERT MICHEL

IPC: H04N11/04 ,  G06T9/00 ,  H04N5/44 ,  H04N7/01 ,  H04N7/26 ,  H04N7/52 ,  H04N11/20

Abstract: The system includes a digital decoding module (30) which provides on-screen display (OSD) and main-picture (I) data streams which are mixed (34) and multiplexed (40). An encoding module (36) contains D/A converters (28,38) and a block (39) which performs common functions for two data stream encoders (27,37). These common functions include the generation of clock and chrominance subcarrier signals and the optimisation of the encoding function by minimising the required number of integrated circuits and connections. The sampling rates of the multiplexer and demultiplexer (41) correspond to twice the control frequency (F) of the mixer.

公开(公告)号：DE69422228T2

公开(公告)日：2001-03-29

申请号：DE69422228

申请日：1994-06-27

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: G06F12/04 ,  G06F13/40 ,  H04N7/26 ,  H04N7/36 ,  H04N7/50 ,  H04N7/24

Abstract: The present invention relates to a processor system comprising a data bus with a fixed size of N bits (D64) connected to a memory (12) for words of n bits by a bus with a size of n bits (D16), where N is a multiple of n and where n is variable. The system comprises means (62) for, on each execution by the processor of an instruction for writing an N-bit word into the memory, successively writing each sub-word of n bits constituting this N-bit word to distinct addresses; and means (60, 64, 65, 66) for, on each execution of an instruction for reading an N-bit word from the memory, successively reading from the said memory at distinct addresses sub-words of n bits, and juxtaposing these sub-words on the bus of fixed size.

公开(公告)号：DE69517718T2

公开(公告)日：2001-02-01

申请号：DE69517718

申请日：1995-02-15

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: G11C7/00 ,  G06F7/78 ,  H04N5/907 ,  H04N7/26 ,  H04N7/32 ,  G06F7/00

Abstract: The circuit includes a double access memory system (10) connected through busses to systems for writing data in an initial order and for reading the data in a predetermined final order. A control register (14) allows memory read operations only when its content is non-zero. The register has its contents decremented at each read operation and incremented by 1 plus the difference between the rank of the input data and the rank of the output data, or zero if the difference is negative. Output data can be read even if all the input data is not available.

公开(公告)号：FR2864320A1

公开(公告)日：2005-06-24

申请号：FR0314960

申请日：2003-12-19

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: G06F5/10 ,  G11C7/10 ,  G11C11/419 ,  G11C8/04

Abstract: The memory has a synchronous RAM (SRAM) (110) with a frequency half of that of the memory and storing simultaneously two words of n-bits received successively on an input (DIN) of the memory. A storage circuit (130) stores a word of n-bits received on the input (DIN) or simultaneously two words of n-bits received from the SRAM. The circuit generates one word at the output of the memory. An independent claim is also included for a process of controlling contents of a first-in first-out memory.

公开(公告)号：DE69429207T2

公开(公告)日：2002-07-18

申请号：DE69429207

申请日：1994-05-20

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: H04N7/26 ,  G06F9/32 ,  G06F9/38 ,  G06F9/46 ,  G06T1/20 ,  G06T9/00

Abstract: The present invention relates to a system for processing compressed image data arriving in packets, these packets being separated by headers comprising parameters. A memory bus (MBUS) is managed by a memory controller (24) in order to exchange data between processing elements and an image memory (15). A pipeline circuit (11, 12, 13) comprises several processing elements and a parameter bus (VLDBUS) serves to supply packets to be processed to the pipeline circuit as well as parameters to elements of the pipeline circuit. This parameter bus is managed by a circuit VLD which receives compressed data from the memory bus and which comprises a header detector in order to supply the parameters to the elements of the pipeline circuit and to other elements of the system which require them.

公开(公告)号：DE69422453D1

公开(公告)日：2000-02-10

申请号：DE69422453

申请日：1994-07-08

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: G11C11/41 ,  G11C7/00 ,  G11C7/10 ,  G11C8/04 ,  G11C8/16 ,  G11C11/417 ,  G11C11/419 ,  G11C8/00 ,  H03K23/54 ,  H03K19/003 ,  G11C19/00

Abstract: The memory (10) includes columns of memory cells with their output connected to an output bus (Bo') via a MOS transistor (M2'). The memory output is set to zero by a MOS transistor (10- 2) connected between the first transistor and earth. The output bus is connected to a voltage (Vdd) via a pre-charge transistor (MP1) whose grid is controlled by a column-read signal (RC). Output transistors (M3) have their grids connected to a bus (RC2) linked to a gate (16). An inverter (18) connects the gate to the output bus (Bo').