公开(公告)号：DE602004014558D1

公开(公告)日：2008-08-07

申请号：DE602004014558

申请日：2004-04-16

Applicant: ST MICROELECTRONICS SA

Inventor： ROBIN FREDERIC ,  ARTIERI ALAIN ,  AUDRAIN STEPHANE ,  DUMAREST JACQUES ,  LEFFTZ VINCENT

IPC: G06F15/167 ,  G06F9/46 ,  H04N7/26

Abstract: The method involves registering a link indicating moment of processing of a message by a sub-system (3) when a counter (5) has null value otherwise registering the link towards following message in the sub-system and incrementing the counter, by a central processor (2). The sub-system reads the link towards the following message if the counter has non-null value and processes parameters of sub-tasks of the following message. An independent claim is also included for an electronic system for execution of concurrent tasks.

公开(公告)号：DE602004001439D1

公开(公告)日：2006-08-17

申请号：DE602004001439

申请日：2004-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: G06F5/06 ,  G06F5/10 ,  G11C7/10 ,  G11C11/419

Abstract: The memory has a synchronous RAM (SRAM) (110) with a frequency half of that of the memory and storing simultaneously two words of n-bits received successively on an input (DIN) of the memory. A storage circuit (130) stores a word of n-bits received on the input (DIN) or simultaneously two words of n-bits received from the SRAM. The circuit generates one word at the output of the memory. An independent claim is also included for a process of controlling contents of a first-in first-out memory.

公开(公告)号：DE69422453T2

公开(公告)日：2000-09-07

申请号：DE69422453

申请日：1994-07-08

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: G11C11/41 ,  G11C7/00 ,  G11C7/10 ,  G11C8/04 ,  G11C8/16 ,  G11C11/417 ,  G11C11/419 ,  G11C8/00 ,  H03K23/54 ,  H03K19/003 ,  G11C19/00

Abstract: The memory (10) includes columns of memory cells with their output connected to an output bus (Bo') via a MOS transistor (M2'). The memory output is set to zero by a MOS transistor (10- 2) connected between the first transistor and earth. The output bus is connected to a voltage (Vdd) via a pre-charge transistor (MP1) whose grid is controlled by a column-read signal (RC). Output transistors (M3) have their grids connected to a bus (RC2) linked to a gate (16). An inverter (18) connects the gate to the output bus (Bo').

公开(公告)号：FR2922386A1

公开(公告)日：2009-04-17

申请号：FR0758346

申请日：2007-10-16

Applicant: ST MICROELECTRONICS SA

Inventor： LASBOUYGUES BENOIT ,  CLERC SYLVAIN ,  ARTIERI ALAIN ,  ZOUNES THOMAS ,  JACQUET FRANCOIS

IPC: H03K5/05

Abstract: L'invention concerne un générateur d'impulsions de synchronisation destinées à au moins deux registres, comprenant une première entrée (CK) destinée à recevoir un signal d'horloge et au moins une sortie (CP) destinée à fournir les impulsions sur l'entrée d'horloge desdits registres, caractérisé en ce qu'il comporte au moins une deuxième entrée (SETH) destinée à recevoir un signal de forçage de la sortie, indépendamment du signal d'horloge, pour rendre transparents lesdits registres.

公开(公告)号：DE69429207D1

公开(公告)日：2002-01-10

申请号：DE69429207

申请日：1994-05-20

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: H04N7/26 ,  G06F9/32 ,  G06F9/38 ,  G06F9/46 ,  G06T1/20 ,  G06T9/00

Abstract: The present invention relates to a system for processing compressed image data arriving in packets, these packets being separated by headers comprising parameters. A memory bus (MBUS) is managed by a memory controller (24) in order to exchange data between processing elements and an image memory (15). A pipeline circuit (11, 12, 13) comprises several processing elements and a parameter bus (VLDBUS) serves to supply packets to be processed to the pipeline circuit as well as parameters to elements of the pipeline circuit. This parameter bus is managed by a circuit VLD which receives compressed data from the memory bus and which comprises a header detector in order to supply the parameters to the elements of the pipeline circuit and to other elements of the system which require them.

公开(公告)号：DE69419663D1

公开(公告)日：1999-09-02

申请号：DE69419663

申请日：1994-05-20

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

Abstract: The present invention relates to a processor architecture for executing a current task from a plurality of possible tasks. The architecture comprises: a plurality of instruction pointers (IP) associated respectively with the possible tasks and each containing the address of the current instruction to be executed of the associated task, one only of these pointers being capable of being enabled at a time in order to supply its contents as address to the memory; a priority level decoder (18) assigning a predetermined priority level to each enquiry signal and enabling the instruction pointer associated with the active enquiry signal of highest priority level; and means (20) for incrementing the contents of the enabled instruction pointer and for reinitialising it at the start address of the associated program when its contents reach the finish address of the associated program.

公开(公告)号：FR2922386B1

公开(公告)日：2013-08-30

申请号：FR0758346

申请日：2007-10-16

Applicant: ST MICROELECTRONICS SA

Inventor： LASBOUYGUES BENOIT ,  CLERC SYLVAIN ,  ARTIERI ALAIN ,  ZOUNES THOMAS ,  JACQUET FRANCOIS

IPC: H03K5/05

公开(公告)号：DE69533781D1

公开(公告)日：2004-12-30

申请号：DE69533781

申请日：1995-03-22

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: H04N5/14 ,  G06T1/20 ,  G06T5/20 ,  H04N7/26 ,  H04N7/30 ,  H04N7/50 ,  H04N7/36

Abstract: The filter includes an input bus (B0,B1) which receives the pixels of n successive columns from a matrix. Delay circuits (20,21) receive the respective pixels from the input bus and introduce a delay into each column which results in 2n pixels being simultaneously transmitted at successive outputs of the delay circuits and the input bus. There are n adders (23,24) which are connected so that the ith adder receives the ith set of 2n pixels at a first input and the (i+1)th set of 2n pixels at a second input. The adders are connected to a switch which receives at a first input one from the ith to the (i+n-1)th set of 2n pixels. The second input receives one from the (i+1)th to the (i+n)th set of 2n pixels. The inputs are determined according to a image matrix position vector.

公开(公告)号：FR2854263A1

公开(公告)日：2004-10-29

申请号：FR0305064

申请日：2003-04-24

Applicant: ST MICROELECTRONICS SA

Inventor： ROBIN FREDERIC ,  ARTIERI ALAIN ,  AUDRAIN STEPHANE ,  DUMAREST JACQUES ,  LEFFTZ VINCENT

IPC: G06F9/46 ,  H04N7/26 ,  G06F15/167

Abstract: The method involves registering a link indicating moment of processing of a message by a sub-system (3) when a counter (5) has null value otherwise registering the link towards following message in the sub-system and incrementing the counter, by a central processor (2). The sub-system reads the link towards the following message if the counter has non-null value and processes parameters of sub-tasks of the following message. An independent claim is also included for an electronic system for execution of concurrent tasks.

公开(公告)号：DE69429374D1

公开(公告)日：2002-01-17

申请号：DE69429374

申请日：1994-07-08

Applicant: ST MICROELECTRONICS SA

Inventor： ARTIERI ALAIN

IPC: G11C11/41 ,  G11C7/00 ,  G11C7/10 ,  G11C8/04 ,  G11C8/16 ,  G11C11/417 ,  G11C11/419 ,  G11C8/00 ,  H03K23/54 ,  H03K19/003 ,  G11C19/00

Abstract: The memory (10) includes columns of memory cells with their output connected to an output bus (Bo') via a MOS transistor (M2'). The memory output is set to zero by a MOS transistor (10- 2) connected between the first transistor and earth. The output bus is connected to a voltage (Vdd) via a pre-charge transistor (MP1) whose grid is controlled by a column-read signal (RC). Output transistors (M3) have their grids connected to a bus (RC2) linked to a gate (16). An inverter (18) connects the gate to the output bus (Bo').