公开(公告)号：FR2800199B1

公开(公告)日：2002-03-01

申请号：FR9913379

申请日：1999-10-21

Applicant: ST MICROELECTRONICS SA

Inventor： CIAVATTI JEROME

IPC: H01L21/8242

公开(公告)号：FR2800199A1

公开(公告)日：2001-04-27

申请号：FR9913379

申请日：1999-10-21

Applicant: ST MICROELECTRONICS SA

Inventor： CIAVATTI JEROME

IPC: H01L21/8242

Abstract: Preparation of a dynamic random access memory device constituted of cells each comprising a MOS command transistor and a condenser comprising, after formation of the command transistor: (a) forming an isolated thick layer; (b) depositing a thin layer of dielectric material; (c) depositing a second conductive material; (d) leveling by mechanical-chemical polishing; and (e) depositing a metallic material directly on the second conductive material and the thick isolating layer. Preparation of a dynamic random access memory device constituted of cells each comprising a MOS command transistor and a condenser comprising, after formation of the command transistor: (a) forming an isolated thick layer (205; 205-212) of openings where the walls are recovered with a first conductive material (206); (b) depositing a thin layer of dielectric material (208) over the structure; (c) depositing a second conductive material (209) to fill completely the opening and overflow; (d) leveling by mechanical-chemical polishing, the second conductive material to the upper surface of the parts of the dielectric layer resting on the parts of the isolating layer, between two openings; and (e) depositing a metallic material (211-1; 313-1) directly on the second conductive material and the thick isolating layer to interconnect at least two openings filled with second conductive material. An Independent claim is included for the dynamic random access memory comprising cells each comprising a MOS command transistor and a condenser.

公开(公告)号：FR2790597A1

公开(公告)日：2000-09-08

申请号：FR9901892

申请日：1999-02-12

Applicant: ST MICROELECTRONICS SA

Inventor： CIAVATTI JEROME

IPC: H01L21/8242 ,  H01L21/28

Abstract: The capacitor comprises an electrode (6) in the form of a recess with generally horizontal bottom and vertical walls, which is in electrical contact with a conducting pad (3). The conducting pad (3) is with upper surface at the level of an insulator layer (2), which is with a recess complementary to a projecting part (8) of the conducting pad. The manufacturing method includes the formation of an opening in the first insulator layer (2) to expose a region of substrate (1), the deposition and print of the first conductor layer in a manner to form the conducting pad (3), the deposition of the second insulator layer (4), the formation of an opening in the first and second insulator layers to make the conducting pad projecting with respect to the neighboring first insulator layer, the deposition of the second conductor layer (6), the etching of the second conductor layer to remove the horizontal parts from the second insulator layer, the depositing of a thin dielectric layer, and the deposition and print of the third conductor layer. The electrode (6) is in the form of a layer of polycrystalline silicon. The conducting pad (3) is formed of tungsten or polycrystalline silicon. The insulator layers (2,4) are formed of silicon oxide. The print of the second conductor layer is by the mechanical-chemical print method.