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    3.
    发明专利
    未知

    公开(公告)号：DE60019483D1

    公开(公告)日：2005-05-25

    申请号：DE60019483

    申请日：2000-02-11

    Applicant: ST MICROELECTRONICS SA

    Inventor： CIAVATTI JEROME

    IPC: H01L21/8242 ,  H01L21/00

    Abstract: The capacitor comprises an electrode (6) in the form of a recess with generally horizontal bottom and vertical walls, which is in electrical contact with a conducting pad (3). The conducting pad (3) is with upper surface at the level of an insulator layer (2), which is with a recess complementary to a projecting part (8) of the conducting pad. The manufacturing method includes the formation of an opening in the first insulator layer (2) to expose a region of substrate (1), the deposition and print of the first conductor layer in a manner to form the conducting pad (3), the deposition of the second insulator layer (4), the formation of an opening in the first and second insulator layers to make the conducting pad projecting with respect to the neighboring first insulator layer, the deposition of the second conductor layer (6), the etching of the second conductor layer to remove the horizontal parts from the second insulator layer, the depositing of a thin dielectric layer, and the deposition and print of the third conductor layer. The electrode (6) is in the form of a layer of polycrystalline silicon. The conducting pad (3) is formed of tungsten or polycrystalline silicon. The insulator layers (2,4) are formed of silicon oxide. The print of the second conductor layer is by the mechanical-chemical print method.

    4.
    发明专利
    未知

    公开(公告)号：FR2816110B1

    公开(公告)日：2003-03-21

    申请号：FR0013854

    申请日：2000-10-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： CIAVATTI JEROME

    IPC: H01L21/60 ,  H01L21/8242

    Abstract: A method for manufacturing a DRAM cell including two active word lines having a drain region and distinct source regions, including, after the forming of insulated conductive lines, the steps of: depositing a first, then a second selectively etchable insulating layers; etching the second insulating layer to only maintain it above conductive lines; depositing and leveling a third insulating layer selectively etchable with respect to at least the second insulating layer; opening the first and third insulating layers to expose the drain region and an insulating trench; filling the previously-formed opening with a conductive material; polishing the entire structure; and depositing a fourth insulating layer, selectively etchable with respect to the third insulating layer.

    Fabrication of a dynamic random access memory cell
    8.
    发明专利
    Fabrication of a dynamic random access memory cell 未知

    公开(公告)号：FR2816110A1

    公开(公告)日：2002-05-03

    申请号：FR0013854

    申请日：2000-10-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： CIAVATTI JEROME

    IPC: H01L21/60 ,  H01L21/8242

    Abstract: The fabrication of a DRAM cell incorporating two word lines (WL2, WL3) having a drain region (9) and some distinct source regions (10) comprises, after the formation of insulated conducting lines (WL1, WL2, WL3, WL4), the following steps: (a) depositing two insulated selectively engravable layers (15, 16); (b) engraving the second layer to retain it only above the conducting lines; (c) depositing and flattening a third insulating layer (11) selectively engravable with respect to the second insulated layer; (d) opening the first and third insulated layers to expose the drain region as well as an insulation trench (4); (e) filling this opening with a conducting material (18); (f) and depositing a fourth insulated layer (19), selectively engravable with respect to the third insulated layer. An Independent claim is also included for a DRAM memory cell structure fabricated by this method.

    10.
    发明专利
    未知

    公开(公告)号：FR2790597B1

    公开(公告)日：2003-08-15

    申请号：FR9901892

    申请日：1999-02-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： CIAVATTI JEROME

    IPC: H01L21/8242 ,  H01L21/28

    Abstract: The capacitor comprises an electrode (6) in the form of a recess with generally horizontal bottom and vertical walls, which is in electrical contact with a conducting pad (3). The conducting pad (3) is with upper surface at the level of an insulator layer (2), which is with a recess complementary to a projecting part (8) of the conducting pad. The manufacturing method includes the formation of an opening in the first insulator layer (2) to expose a region of substrate (1), the deposition and print of the first conductor layer in a manner to form the conducting pad (3), the deposition of the second insulator layer (4), the formation of an opening in the first and second insulator layers to make the conducting pad projecting with respect to the neighboring first insulator layer, the deposition of the second conductor layer (6), the etching of the second conductor layer to remove the horizontal parts from the second insulator layer, the depositing of a thin dielectric layer, and the deposition and print of the third conductor layer. The electrode (6) is in the form of a layer of polycrystalline silicon. The conducting pad (3) is formed of tungsten or polycrystalline silicon. The insulator layers (2,4) are formed of silicon oxide. The print of the second conductor layer is by the mechanical-chemical print method.

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