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    12.
    发明专利
    未知

    公开(公告)号：FR2797086B1

    公开(公告)日：2001-10-12

    申请号：FR9910090

    申请日：1999-07-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C17/18 ,  H03K19/00 ,  H03K19/0185 ,  G11C17/16

    Abstract: A one-time programmable cell including an inverter providing a logic state according to the state of the cell; a fuse coupled between a first supply voltage and the inverter input; and a current source coupled between the fuse and a second supply voltage. The inverter is supplied from the second supply voltage through a first diode-connected transistor and the current source is formed of a second transistor controlled by the inverter output, this second transistor having a threshold voltage greater than that of the first transistor.

    13.
    发明专利
    未知

    公开(公告)号：FR2801410A1

    公开(公告)日：2001-05-25

    申请号：FR9914792

    申请日：1999-11-24

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/412

    Abstract: The dynamic random access memory device comprises a planar memory incorporating an array of memory cells, a read/write amplifier (AMLE) connected to the extremity of each column of array, a pair of input/output lines (IO, ION) associated with the array, and a stage of cache-memory (MCH) connected to each amplifier and located in the immediate vicinity of amplifier. The stage of cache-memory comprises a static random access memory cell connected between the read/write amplifier (AMLE) and the pair of input/output lines (IO, ION). The static random access memory cell comprises two memory transistors (TM3, TM4), a pair of first access transistors (T9, T10) connected between the amplifier and the memory transistors, and a pair of second access transistors (TA1, TA2) connected respectively between the pair of input/output lines and the memory transistors. The holding means comprise the access transistors (TA1, TA2) capable to maintain a binary datum in the cell, preliminary transferred from a memory cell via the amplifier. The access transistors (TA1, TA2) have the leakage currents more significant than other transistors of the cell. In the second variant of device, the static random access memory cell comprises a pair of auxiliary transistors, which are constantly in off-state and connected between the memory transistors and a supply voltage; the auxiliary transistors have the leakage currents more significant than other transistors of the cell, and the holding means comprise the auxiliary transistors. The access transistors (TA1, TA2) and the auxiliary transistors have the length of channel and the thickness of gate oxide layer smaller than those of other transistors of the cell. The holding means comprise a voltage regulator capable to apply a substrate effect voltage to each transistor of the cell, with the exception of second access transistors and auxiliary transistors, in order to obtain the leakage current of each auxiliary transistor or second access transistor higher, preferentially at least ten times higher, than the leakage currents of other transistors of the cell. The holding means comprise the means for the application of different biasing voltages to the nodes of second access transistors or auxiliary transistors in order to obtain the drain-source currents higher, preferentially at least ten times higher, that the leakage currents of other transistors of the cell. The array of memory cells comprises seveal sub-arrays respectively associated with the pairs of different input/output lines, where all stages of cache-memory associated with one sub-array are all connected in parallel to the pair of input/output lines associated with the sub-array. The planar memory comprises a block-memory formed by two arrays of memory cells, and the amplifiers, the stages of cache-memory and the pairs of input/output lines are common to both arrays. The planar memory comprises several block-memories, and the pairs of input/output lines are common to different block-memories. The device comprises at least two stages of cache-memory respectively connected in parallel to each amplifier. The method for reading a datum stored in a memory cell of planar memory includes the transfer of datum into the cell of static random access memory of the stage of cache-memory associated with the column containing the cell, and then reading the content of cell by the intermediary of input/output lines.

    15.
    发明专利
    未知

    公开(公告)号：FR2797117A1

    公开(公告)日：2001-02-02

    申请号：FR9910043

    申请日：1999-07-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: H03K3/012 ,  H03K3/03 ,  H03B5/32

    Abstract: The oscillator with quartz crystal (10) comprises an inverter (8) with complementary transistors (MN1, MP1) connected between high (Vdd) and low (GND) potentials of power supply by the intermediary of two resistances, which are constituted by lossy capacitors (18C, 20C) with higher than normal leakage currents, and an amplifier (22) for delivering logic stages according to output levels of the oscillator. The amplifier (22) comprises a number of stages, each containing two transistors with opposite conductivity type channels connected in series between high and low potentials of power supply, where the gate of first transistor of each stage is connected to the output of preceding stage, and the gates of second transistors of two consecutive stages are connected respectively to the input and the output of the inverter (8).

    18.
    发明专利
    未知

    公开(公告)号：FR2784219A1

    公开(公告)日：2000-04-07

    申请号：FR9811715

    申请日：1998-09-16

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/02 ,  G11C11/401

    Abstract: The memory realized in an integrated circuit chip (2') comprises a matrix network of cells divided in sections (S), rows of amplifiers for column decoding (CDEC) with outputs interconnected to decoded bit lines, each comprising two perpendicular sections, one in the row direction for connecting directly each decoded bit line to the input/output (I/O) stage at the extremity of rows. The circuits for row decoding (RDEC), predecoding (PREDEC), input/output (I/O), and control (CONTROL) are located in the same section as the bus for address (ADD), data (DATA) and control (CTR) signals. The change of direction within two sections of the bit line is carried out without active element, by direct interconnection. The memory cell contains a transistor connected to a capacitor, and the amplifier for column decoding is directly connected to the local bit line interconnecting the drains of transistors in the same section. The circuits (PREDEC, RDEC, I/O) can be located on both sides of the integrated circuit chip. The number of rows of memory cells per section is selected to have the signal/noise ratio higher than 1/10 at inputs of amplifiers for column decoding.

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