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    MEMORY CIRCUIT CONSTRUCTION
    1.
    发明专利
    MEMORY CIRCUIT CONSTRUCTION 失效

    公开(公告)号：JP2000133789A

    公开(公告)日：2000-05-12

    申请号：JP29380599

    申请日：1999-10-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： JAOUEN HERVE ,  FERRANT RICHARD

    IPC: G11C11/401 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a DRAM with which a power source and a ground are protected from charging variation of a memory element. SOLUTION: Cells 1-n of a memory circuit construction include MOS transistors M1-Mn and capacitors C1-Cn. An electrode 311 is connected in common to all cells of the same line and is covered with an insulator 312. The insulator is covered with independent conductive elements 313-1 and 313-2 which are diffused on the same horizontal plane. The two adjacent elements 313-1 and 313-2 are respectively biased at a high potential or a low potential. The low potential is a reference potential of the circuit, in which the cells are formed. The high potential is a potential Vdd for writing in the memory cells.

    DYNAMIC MEMORY CIRCUIT INCLUDING SPARE CELL
    2.
    发明专利
    DYNAMIC MEMORY CIRCUIT INCLUDING SPARE CELL 审中-公开

    公开(公告)号：JP2002042481A

    公开(公告)日：2002-02-08

    申请号：JP2001196763

    申请日：2001-06-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04

    Abstract: PROBLEM TO BE SOLVED: To provide a row constituting of spare memory cells which is realized more simply and more effectively in a memory circuit, and to provide a circuit in which the occupied surface area is smaller than a conventional circuit having spare cells. SOLUTION: This dynamic memory circuit includes memory cells arranged in rows and columns, each row which can be started by a word line, each column fomed by cells connected to first and second bit lines, at least one spare row formed by static memory cells being coped so as to be started to replace a memory cell row, and each spare cell connected to the first and the second bit lines of a column of a circuit.

    AMPLIFIER FOR READING STORAGE CELLS WITH EXCLUSIVE-OR TYPE FUNCTION
    3.
    发明申请
    AMPLIFIER FOR READING STORAGE CELLS WITH EXCLUSIVE-OR TYPE FUNCTION 审中-公开
    用于读取具有独特或类型功能的存储单元的放大器

    公开(公告)号：WO0249034A2

    公开(公告)日：2002-06-20

    申请号：PCT/FR0104004

    申请日：2001-12-14

    Applicant: ST MICROELECTRONICS SA ,  FERRANT RICHARD

    Inventor： FERRANT RICHARD

    IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4091

    CPC classification number: G11C11/4091 ,  G11C7/062 ,  G11C7/1006

    Abstract: The invention concerns an amplifier (1), capable of being controlled by an activation signal, for reading storage cells of a crossbar network comprising, for each column, a direct bit line (BLdi) and a reference bit line (BLri), the amplifier being common to two columns and producing an OR-Exclusive type combination of the states of the cells read in said two columns.

    Abstract translation: 本发明涉及一种能够被激活信号控制的放大器（1），用于读取交叉开关网络的存储单元，其包括针对每列的直接位线（BLdi）和参考位线（BLri），放大器 对于两列是共同的，并且产生在所述两列中读取的单元的状态的OR-Exclusive类型组合。

    5.
    发明专利
    未知

    公开(公告)号：FR2794301B1

    公开(公告)日：2004-10-08

    申请号：FR9906797

    申请日：1999-05-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD ,  JACQUET FRANCOIS

    IPC: H02M3/07

    Abstract: At a charging phase, a capacitor (PC) is charged through two complementary charging transistors (TR1, TR2) connected in series to a first terminal (T1) of the capacitor (PC). At a voltage multiplication phase, an input voltage (Vdd) is delivered to the second terminal (T2) of the capacitor and an output voltage (Vout), increased with respect to the input voltage, is recovered at the first terminal (T1) of the, capacitor, and the capacitor is discharged during a discharging phase. During three phases, the substrate (BK2) of the charging transistor (TR2) directly connected to the first terminal (T1) of the capacitor is slaved to the source (S2) of this same charging transistor (TR2), while still keeping the source-substrate junction and the drain-substrate junction of this charging transistor (TR2) reverse-biased.

    7.
    发明专利
    未知

    公开(公告)号：DE60002403T2

    公开(公告)日：2004-03-25

    申请号：DE60002403

    申请日：2000-07-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: H03K3/012 ,  H03K3/03

    Abstract: The oscillator with quartz crystal (10) comprises an inverter (8) with complementary transistors (MN1, MP1) connected between high (Vdd) and low (GND) potentials of power supply by the intermediary of two resistances, which are constituted by lossy capacitors (18C, 20C) with higher than normal leakage currents, and an amplifier (22) for delivering logic stages according to output levels of the oscillator. The amplifier (22) comprises a number of stages, each containing two transistors with opposite conductivity type channels connected in series between high and low potentials of power supply, where the gate of first transistor of each stage is connected to the output of preceding stage, and the gates of second transistors of two consecutive stages are connected respectively to the input and the output of the inverter (8).

    9.
    发明专利
    未知

    公开(公告)号：DE60002403D1

    公开(公告)日：2003-06-05

    申请号：DE60002403

    申请日：2000-07-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: H03K3/012 ,  H03K3/03

    Abstract: The oscillator with quartz crystal (10) comprises an inverter (8) with complementary transistors (MN1, MP1) connected between high (Vdd) and low (GND) potentials of power supply by the intermediary of two resistances, which are constituted by lossy capacitors (18C, 20C) with higher than normal leakage currents, and an amplifier (22) for delivering logic stages according to output levels of the oscillator. The amplifier (22) comprises a number of stages, each containing two transistors with opposite conductivity type channels connected in series between high and low potentials of power supply, where the gate of first transistor of each stage is connected to the output of preceding stage, and the gates of second transistors of two consecutive stages are connected respectively to the input and the output of the inverter (8).

    Dynamic random-access memory (DRAM) with stage for restoring memory cells, comprising three double-gate p-MOS transistors connected between higher supply voltage and pair of bit lines
    10.
    发明专利
    Dynamic random-access memory (DRAM) with stage for restoring memory cells, comprising three double-gate p-MOS transistors connected between higher supply voltage and pair of bit lines 未知

    公开(公告)号：FR2819091A1

    公开(公告)日：2002-07-05

    申请号：FR0017294

    申请日：2000-12-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD ,  JACQUET FRANCOIS

    IPC: G11C11/406 ,  G11C11/401 ,  G11C11/402

    Abstract: The memory store comprises a memory array (MA) of cells (2) laid out in rows and columns, where for each column there is a sense amplifier (SA) used in write operation for polarizing a selection of cells to either a supply voltage (Vdd) or to a lower voltage, and in read operation for determining if the level of stored charge is higher or lower than a predetermined level, an isolation stage (3) for separating the memory array from the read/write circuit, and a restoring stage (19) for increasing the charge stored in memory cell beyond the two pre-determined levels. The restoring stage (19) comprises a double-gate p-MOS transistor (P24) connected between a higher supply voltage (VRS) terminal and a node of interconnection of two double-gate p-MOS transistors (P22,P23) whose sources are cross-connected to the gates and constitute the input/output terminals (OUT20,OUT21). The isolation stage (3) comprises two double-gate n-MOS transistors (N10,N11). The precharge stage (16) comprises two double-gate n-MOS transistors (N17,N18). The precharging ad balancing stage (12) for the sense amplifier (SA) comprises three p-MOS transistors (P13,P14,P15) with common gate, where the midpoint of the pair (P13,P14) is connected to the supply voltage (Vdd) terminal and the third transistor (P15) short-circuits the sense amplifier terminals (SA1,SA2). The method for writing data in memory cells includes the polarization of the isolation stage (3) so that it is partially open and the validation of the restoring stage (19). The method for restoring data in memory cell includes the polarization of the isolation stage (3) so that it is completely open, and the validation of the restoring stage (19). The method for controlling the memory cell includes the provision of a control signal (BLPASS) having three levels, where the first level activates the complete opening of the isolation stage, the second level completely inhibits the isolation stage, and the third level activates or inhibits each double-gate n-MOS transistor (N10,N11) according to the state of the sense amplifier input/output terminal (SA1,SA2).

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