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    13.
    发明专利
    未知

    公开(公告)号：DE69512456D1

    公开(公告)日：1999-11-04

    申请号：DE69512456

    申请日：1995-04-06

    Applicant: ST MICROELECTRONICS SA

    Inventor： COSTABELLO CLAUDE ,  GAULTIER JEAN-MARIE

    IPC: G11C17/00 ,  G11C16/02 ,  G11C16/16 ,  G11C16/06

    Abstract: The method involves using a non-volatile memory (11) and address circuits (121-123). The non-volatile integrated circuit memory is divided into N sectors (S0- S31), the sectors being separately addressable by address circuits (123). The N sectors are arranged into m groups of n sectors each, the cells of each sector being selectable by other address circuits (121,122). An erasure pulse is applied simultaneously to all the sectors, or to the sectors of a group. The erasure of each sector is then verified. Repeated erasure pulses are applied, until all the sectors, or all the sectors of the group pass the verification test. Sectors are locked as it is detected that they have been successfully erased, so that in each cycle the number of sectors to be erased is reduced.

    15.
    发明专利
    未知

    公开(公告)号：DE69933401T2

    公开(公告)日：2007-08-16

    申请号：DE69933401

    申请日：1999-01-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： GAULTIER JEAN-MARIE

    IPC: H04L25/45 ,  G06F13/42

    Abstract: The message begins with a start bit (START) which is followed by the useful information (INFO) and a parity bit (CHECK). Two further bits (BS1,BS2) are included which indicate the end of the message and also the type of information carried such as command, address, data and high and low value digits. Individual stages of an overall instruction such as read or write may then be individually checked

    17.
    发明专利
    未知

    公开(公告)号：DE69925394D1

    公开(公告)日：2005-06-30

    申请号：DE69925394

    申请日：1999-02-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： GAULTIER JEAN-MARIE

    IPC: G06K7/00 ,  G07C9/00 ,  G06K7/10

    Abstract: A method for the identification of electronic cards within an investigation zone includes encoding an identification number on M bits distributed into P blocks of Q bits assigned to each electronic card. Reconstruction of the block-by-block identification numbers is performed according to a tree-like iterative algorithm. In this iterative algorithm, each iteration includes a step for transmitting an interrogation message intended for certain electronic cards. Each iteration also includes a step for transmitting, by each of the electronic cards, a response message having a service bit in a narrow time window whose positioning in a sequence of 2Q successive identical windows indicates the value of an as yet unidentified block of bits of its identification number.

    19.
    发明专利
    未知

    公开(公告)号：DE69509965D1

    公开(公告)日：1999-07-08

    申请号：DE69509965

    申请日：1995-03-20

    Applicant: ST MICROELECTRONICS SA

    Inventor： ROUY OLIVIER ,  GAULTIER JEAN-MARIE

    IPC: G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  G06F11/20

    Abstract: The integrated circuit memory is arranged in rows and columns and includes a redundant fuse device for recording the addresses of defective rows and columns. This is used to select a redundant element when a defective element is detected. The address code (AO, An) of each defective row or column is recorded in a column of memory cells (ELFO, ELFm) which comprises two cells (COO, CIOO) recoding the number and its complement. When the memory cells are read, the appropriate cells are selected by activation with current, leaving aside those known to be defective.

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