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    11.
    发明专利
    未知

    公开(公告)号：DE602006003134D1

    公开(公告)日：2008-11-27

    申请号：DE602006003134

    申请日：2006-06-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： MEYER JACQUES

    IPC: H03D3/00

    Abstract: The method involves receiving, in receiver of a digital communication system, a known training sequence according to pi /2 binary phase shift keying (BPSK) or modulation phase shift keying (MDP2) type modulation. The sequence is demodulated, and a differential correlation is calculated on a set of N received samples and of N presumably sent samples to generate a result. The result is used to detect the start of a frame and a sign for controlling a spectral inversion in the received sequence. Independent claims are also included for the following: (1) a receiver for a digital communication system comprising a demodulator spectral inversion device (2) a digital communication system comprising a receiver comprising a demodulator spectral inversion device.

    12.
    发明专利
    未知

    公开(公告)号：FR2837338B1

    公开(公告)日：2005-05-06

    申请号：FR0203256

    申请日：2002-03-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： MEYER JACQUES

    IPC: H03D3/00 ,  H04L27/00 ,  H04L27/38

    Abstract: The analog to digital converters (34,42) output signals (I',Q'), based on digitized output signals (Ia',Qa') of demodulators (28,32), that are input to correcting circuit (36) to obtain output signals (I'',Q''). The output signals (I''',Q''') of derotator (40) is obtained, by input of correcting circuit and feedback loop (38) output signals. An Independent claim is also included for method for demodulating carriers in quadrature modulation by two signal.

    13.
    发明专利
    未知

    公开(公告)号：FR2781626B1

    公开(公告)日：2003-02-07

    申请号：FR9809578

    申请日：1998-07-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： MEYER JACQUES

    IPC: H04L27/00 ,  H04L27/227 ,  H04L27/22 ,  H04L1/20

    Abstract: The process uses multiplication of vector angle and analysis of derivative to locate error. The procedure provides an estimation of the frequency error of a demodulator which is used to reconstruct two binary signals (I,Q) carried on two carriers of the same frequency but operating in phase quadrature. The procedure comprises the first stage of forming vectors having the successive pairs of values (I,Q) of two binary signals as components. The second stage includes applying to each vector a transformation which multiplies its angle by four, at least when it is equal to a multiple of /4, whilst retaining its modulus. The third stage includes calculating the average (x1,y1) of the transformed vectors. The frequency error is obtained as being equal to the angular derivative of the average vector.

    14.
    发明专利
    未知

    公开(公告)号：DE69522156T2

    公开(公告)日：2002-05-02

    申请号：DE69522156

    申请日：1995-06-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： MEYER JACQUES

    IPC: G06F11/10 ,  H03M13/00 ,  H03M13/15 ,  H04B14/04

    Abstract: The Reed Solomon input code (A203..A0) is input to a parallel set of multiplier stages. Each multiplier (44) multiplies the input digital coding by a root (Alpha) of the polynomial Reed-Solomon equation. The roots produce a higher order polynomial equation, and separate out each level of the equation. The outputs are compared with a counter circuit (12-14) which takes the polynomial levels and produces errors for that level of the equation.

    16.
    发明专利
    未知

    公开(公告)号：DE69721406T2

    公开(公告)日：2004-03-18

    申请号：DE69721406

    申请日：1997-07-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： MEYER JACQUES

    IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29

    Abstract: The calculation circuit (10) used, is associated with the first part (14) of a fast memory in which the horizontal and vertical syndromes of the nth. frame are stored while a second part (15) of the fast memory stores the (n-1)th. frame values to present to an error calculation circuit (17). The errors in value and position of the (n-1)th. and (n-2)th. frame are then stored in respective memory regions (19, 20). Both pairs of regions are used cyclically. The frames are also stored in a slow memory (12) and passed to a correction circuit (21) which rectifies the frames according to the stored error information. Flags indicate no errors, excessive errors or several errors and the correction procedure followed in the last instance.

    17.
    发明专利
    未知

    公开(公告)号：FR2817091B1

    公开(公告)日：2003-03-21

    申请号：FR0015078

    申请日：2000-11-22

    Applicant: ST MICROELECTRONICS SA

    Inventor： MEYER JACQUES

    IPC: H03M5/14 ,  H03M13/23 ,  H03M13/27 ,  H03M13/29 ,  H03M13/33 ,  H04L1/00

    Abstract: The invention concerns a data transmission device comprising a turbo coder ( 22 ) comprising an interleaver operating on two interleaving blocks and means ( 26 ) for producing symbols from said codes (D, Y 1 , Y 2 ) supplied by the turbo coder The device comprises means ( 28 ) for inserting a synchronising sequence into said symbols at a site having a predetermined relationship position relative to the symbols produced with the codes associated with a common interleaving block.

    18.
    发明专利
    未知

    公开(公告)号：DE69528796D1

    公开(公告)日：2002-12-19

    申请号：DE69528796

    申请日：1995-06-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： MEYER JACQUES

    IPC: G06F11/10 ,  H03M13/00 ,  H03M13/15 ,  H04B14/04

    Abstract: Two registers and counters are set up. The first having a register R and register Lambda with a counter dR. The second has a register Q and register U with a second counter dQ. The polynomial coefficients to be tested are stored in descending order, with the counter dQ initialised to 2t-1 and counter dR to 2t. (2t-1) steps are carried out and 1) If the counter contents are equal, and the register R is null a set of mathematical transforms are carried out, with the counters decremented. 2) If the counter contents in counter dR are smaller than dQ, then the counter contents are exchanged, and the mathematical transforms carried out as before. At the end of the process, the errors are found in the registers.

    19.
    发明专利
    未知

    公开(公告)号：DE69526887T2

    公开(公告)日：2002-11-14

    申请号：DE69526887

    申请日：1995-08-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： MEYER JACQUES

    IPC: G06F11/10 ,  G06F7/72 ,  H03M13/00

    Abstract: A number (x) of n bits belonging to a Galois group of 2n = N + 1 elements is fed to a unit (10) which raises it to a power t = 2n/2. The raised number (x ) and the original number (x) are multiplied together in a multiplier (12). The product (x ) is inverted in an inversion unit (INV) (14) to form the reciprocal (x t ). This quantity is supplied to a further multiplier (16) together with the raised number (x ) to produce x = x which is the required number.

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