公开(公告)号：JP2007020169A

公开(公告)日：2007-01-25

申请号：JP2006183340

申请日：2006-07-03

Applicant: St Microelectronics Sa ,  エスティ マイクロエレクトロニクス エス.エイ.ST Microelectronics S.A.

Inventor： MEYER JACQUES

IPC: H04L27/22

CPC classification number: H04L27/2273 ,  H03D3/00 ,  H04L27/22

Abstract: PROBLEM TO BE SOLVED: To provide a technology capable of momentarily detecting a spectral inversion from a received signal in a pseudo way.
SOLUTION: A process of correction of the spectral inversion for a receiver in a digital communication system: the process allows the reception in the receiver of a training sequence presumably known according to a modulation of type π/2 BPSK or MDP2. The process includes a step of demodulating the training sequence; steps (21, 22, 23) of calculating the differential correlation on a set of N received samples (R
n ) and presumably sent samples (S
n ) to generate a result; and a step of using the result to detect the beginning of the screen and to order a spectral inversion in the chain of reception of the aforementioned receiver before launching the detection of the beginning of the frame. The process can realize automatic process of the spectral inversion by the receiver.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够以伪方式从接收信号瞬时检测频谱反演的技术。 解决方案：数字通信系统中的接收机的频谱反演的校正过程：该过程允许在接收机中接收根据类型π/ 2 BPSK或MDP2可能已知的训练序列。 该过程包括解调训练序列的步骤; 计算一组N个接收样本（R SB> n ）和推测发送的样本（S n ）之间的差分相关性以产生结果的步骤（21,22,23） ; 以及在开始对帧的开始的检测之前，使用结果来检测屏幕的开始并且在上述接收器的接收链中订购频谱反转的步骤。 该过程可以实现接收机的频谱反演的自动处理。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2000041077A

公开(公告)日：2000-02-08

申请号：JP16972099

申请日：1999-06-16

Applicant: ST MICROELECTRONICS SA

Inventor： MEYER JACQUES

IPC: H03L7/095 ,  H04L7/00 ,  H04L27/00 ,  H04L27/22 ,  H04L27/227

Abstract: PROBLEM TO BE SOLVED: To speedily and accurately detect a lock-in state with a simple process by calculating the module of a vector including as components two couples of values of a QPSK demodulator and determining lock-in conditions according to the number of modules different from a threshold. SOLUTION: A computation unit 20 calculates the module of the vector including as components of a couple of Is and Qs value corresponding to a binary value from a demodulator, i.e., the distance (r) between the point corresponding to Is and Qs and the original point of the arrangement, and a comparator 22 compares it with a threshold distance rth stored in a register 24. According to the comparison result, an adder 26 adds +A or -B from a multiplexer 28 and subtract rth to update the rth in the register 24. A respective process is performed as to the number of charges to automatically adjust the ratio of rth and (r) to A/A+B. An analyzing circuit 30 analyzes variation in rth and activates a lock-in signal LCK when a certain condition wherein rth fall within a range of specific noise-to-signal ratios is met.

公开(公告)号：JP2000059449A

公开(公告)日：2000-02-25

申请号：JP20765999

申请日：1999-07-22

Applicant: ST MICROELECTRONICS SA

Inventor： MEYER JACQUES

IPC: H04L27/22 ,  H04L27/00 ,  H04L27/227

Abstract: PROBLEM TO BE SOLVED: To provide an estimation device for frequency error of a QPSK demodulator that is especially reliable, even in the presence of strong noise. SOLUTION: This method for estimating a frequency error of a demodulator that demodulates two binary signals (I, Q) carried on two carriers with a same frequency and a phase difference of a right angle, consists of a step whose vector components are consecutive pairs of the two binary signals (I, Q) are generated, a step where 4 is multiplied with a phase difference angle when it is equal to a multiple of π/4, and conversion which almost preserves the module is applied to each vector, and a step where a means value of the converted vectors is calculated. A frequency error is obtained as the derivative of an angle of the mean vector.

公开(公告)号：GB2387284B

公开(公告)日：2005-08-10

申请号：GB0305686

申请日：2003-03-12

Applicant: ST MICROELECTRONICS SA

Inventor： MEYER JACQUES

IPC: H03D3/00 ,  H04L27/00 ,  H04L27/38 ,  H03D1/22

Abstract: The analog to digital converters (34,42) output signals (I',Q'), based on digitized output signals (Ia',Qa') of demodulators (28,32), that are input to correcting circuit (36) to obtain output signals (I'',Q''). The output signals (I''',Q''') of derotator (40) is obtained, by input of correcting circuit and feedback loop (38) output signals. An Independent claim is also included for method for demodulating carriers in quadrature modulation by two signal.

公开(公告)号：FR2855001A1

公开(公告)日：2004-11-19

申请号：FR0305749

申请日：2003-05-14

Applicant: ST MICROELECTRONICS SA

Inventor： MEYER JACQUES

IPC: H04L27/18 ,  H04L27/22 ,  H04L27/38

Abstract: The method involves demodulating and decoding a UL signal to regenerate UL information. A set of symbols representative of constellation used in transmission is recoded and formatted for reconstructing a form of continuous waves from the reconstituted symbols. A result of non linear function is subtracted from a composite signal (1) to create a result that is demodulated and decoded to regenerate LL information. The set of symbols representative of constellation is recoded from the regenerated information. The result of non-linear function is obtained by applying a non linear function to the form of continuous waves. An independent claim is also included for a receiver for a digital communication system.

公开(公告)号：GB2387284A

公开(公告)日：2003-10-08

申请号：GB0305686

申请日：2003-03-12

Applicant: ST MICROELECTRONICS SA

Inventor： MEYER JACQUES

IPC: H03D3/00 ,  H04L27/00 ,  H04L27/38 ,  H03D1/22

Abstract: A demodulation circuit for demodulating a received signal quadrature modulated by digital signals includes mixers 26, 30, analog-to-digital converters 34,42, a correcting circuit 36, and a derotator 40. The correcting circuit 36 provides signals to the derotator 40 based on the derotator output signals and on signals provided by the analog-to-digital converters 34, 42.

公开(公告)号：FR2837338A1

公开(公告)日：2003-09-19

申请号：FR0203256

申请日：2002-03-15

Applicant: ST MICROELECTRONICS SA

Inventor： MEYER JACQUES

IPC: H03D3/00 ,  H04L27/00 ,  H04L27/38

Abstract: The analog to digital converters (34,42) output signals (I',Q'), based on digitized output signals (Ia',Qa') of demodulators (28,32), that are input to correcting circuit (36) to obtain output signals (I'',Q''). The output signals (I''',Q''') of derotator (40) is obtained, by input of correcting circuit and feedback loop (38) output signals. An Independent claim is also included for method for demodulating carriers in quadrature modulation by two signal.

公开(公告)号：DE69721406D1

公开(公告)日：2003-06-05

申请号：DE69721406

申请日：1997-07-21

Applicant: ST MICROELECTRONICS SA

Inventor： MEYER JACQUES

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29

Abstract: The calculation circuit (10) used, is associated with the first part (14) of a fast memory in which the horizontal and vertical syndromes of the nth. frame are stored while a second part (15) of the fast memory stores the (n-1)th. frame values to present to an error calculation circuit (17). The errors in value and position of the (n-1)th. and (n-2)th. frame are then stored in respective memory regions (19, 20). Both pairs of regions are used cyclically. The frames are also stored in a slow memory (12) and passed to a correction circuit (21) which rectifies the frames according to the stored error information. Flags indicate no errors, excessive errors or several errors and the correction procedure followed in the last instance.

公开(公告)号：DE69900141T2

公开(公告)日：2001-09-27

申请号：DE69900141

申请日：1999-02-09

Applicant: ST MICROELECTRONICS SA

Inventor： MEYER JACQUES

IPC: G06F13/40

Abstract: Two bus sections (SDA1,SDA2) operating at different voltages (DT1,DT2) may be connected for two way traffic by using a logic module (CL) which consists of interconnected NOR logic gates and voltage impressing transistors (20,21). The two sections of transmission bus may be connected or disconnected by a memory circuit (MEM) which controls a conditional signal sent to the logic module (CL).

公开(公告)号：DE69522156D1

公开(公告)日：2001-09-20

申请号：DE69522156

申请日：1995-06-21

Applicant: ST MICROELECTRONICS SA

Inventor： MEYER JACQUES

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/15 ,  H04B14/04

Abstract: The Reed Solomon input code (A203..A0) is input to a parallel set of multiplier stages. Each multiplier (44) multiplies the input digital coding by a root (Alpha) of the polynomial Reed-Solomon equation. The roots produce a higher order polynomial equation, and separate out each level of the equation. The outputs are compared with a counter circuit (12-14) which takes the polynomial levels and produces errors for that level of the equation.