公开(公告)号：FR2812452A1

公开(公告)日：2002-02-01

申请号：FR0009947

申请日：2000-07-28

Applicant: ST MICROELECTRONICS SA

Inventor： SCHWARTZMANN THIERRY

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/732

Abstract: A method of forming the collector area of a bipolar transistor on a semiconductor substrate, including the steps of forming an insulating trench delimiting an active region, selectively etching the semiconductor material of the active area, performing a selective epitaxy of the semiconductor material, and performing, during the selective epitaxy, a doping of the epitaxial material, this doping being modified during the growth of the epitaxial material.

公开(公告)号：FR2807568A1

公开(公告)日：2001-10-12

申请号：FR0004587

申请日：2000-04-10

Applicant: ST MICROELECTRONICS SA

Inventor： GRIS YVON ,  SCHWARTZMANN THIERRY

IPC: H01L21/761 ,  H01L21/762 ,  H01L21/74

Abstract: A method of forming separate buried layers close to one another in a semiconductor component. This method includes the steps of forming, by implantation, doped areas in a semiconductor substrate; performing an anneal just sufficient to eliminate crystal defects resulting from the implantation; depositing an epitaxial layer; digging trenches delimiting each implanted region; and annealing the buried layers, the lateral diffusion of which is blocked by said trenches, said trenches being deeper than the downward extension of the diffusions resulting from said implantations.

公开(公告)号：FR2779571A1

公开(公告)日：1999-12-10

申请号：FR9807060

申请日：1998-06-05

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  SCHWARTZMANN THIERRY

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737 ,  H01L21/266

Abstract: Selective doping of the intrinsic collector of a vertical bipolar transistor comprises high energy dopant implantation before epitaxy and lower energy and lower dose dopant implantation after epitaxy of a silicon germanium heterojunction base. Selective doping of the intrinsic collector of a vertical bipolar transistor is carried out by (a) forming the intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate; (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well; (c) effecting a first dopant implantation in the intrinsic collector through a first implantation window above the intrinsic collector; (d) forming a silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a silicon and silicon germanium multilayer (8); and (e) effecting a second lower energy and lower dose dopant implantation in the intrinsic collector across the multilayer in a second implantation window located within the first implantation window above the multilayer (8) and self-aligned with the emitter.

公开(公告)号：FR2767964A1

公开(公告)日：1999-03-05

申请号：FR9711019

申请日：1997-09-04

Applicant: ST MICROELECTRONICS SA

Inventor： SCHWARTZMANN THIERRY

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/266

Abstract: During dopant implantation to form a double-diffusion MOS (DMOS) transistor channel zone, the transistor gate is covered with an implantation barrier layer. A DMOS transistor channel zone is produced by dopant implantation into a substrate region adjacent that below the gate (7) to form an implanted zone (80) of conductivity type opposite to that of the source region, while the gate (7) is covered with an implantation barrier layer (110). Preferred Feature: The implantation barrier layer is formed from a resin layer using an etching mask.