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    1.
    发明专利
    未知

    公开(公告)号：DE69935472D1

    公开(公告)日：2007-04-26

    申请号：DE69935472

    申请日：1999-06-03

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  SCHWARTZMANN THIERRY

    IPC: H01L21/331 ,  H01L29/73 ,  H01L21/265 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737

    Abstract: Selective doping of the intrinsic collector of a vertical bipolar transistor comprises high energy dopant implantation before epitaxy and lower energy and lower dose dopant implantation after epitaxy of a silicon germanium heterojunction base. Selective doping of the intrinsic collector of a vertical bipolar transistor is carried out by (a) forming the intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate; (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well; (c) effecting a first dopant implantation in the intrinsic collector through a first implantation window above the intrinsic collector; (d) forming a silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a silicon and silicon germanium multilayer (8); and (e) effecting a second lower energy and lower dose dopant implantation in the intrinsic collector across the multilayer in a second implantation window located within the first implantation window above the multilayer (8) and self-aligned with the emitter.

    4.
    发明专利
    未知

    公开(公告)号：FR2779571B1

    公开(公告)日：2003-01-24

    申请号：FR9807060

    申请日：1998-06-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  SCHWARTZMANN THIERRY

    IPC: H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737 ,  H01L21/266

    Abstract: Selective doping of the intrinsic collector of a vertical bipolar transistor comprises high energy dopant implantation before epitaxy and lower energy and lower dose dopant implantation after epitaxy of a silicon germanium heterojunction base. Selective doping of the intrinsic collector of a vertical bipolar transistor is carried out by (a) forming the intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate; (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well; (c) effecting a first dopant implantation in the intrinsic collector through a first implantation window above the intrinsic collector; (d) forming a silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a silicon and silicon germanium multilayer (8); and (e) effecting a second lower energy and lower dose dopant implantation in the intrinsic collector across the multilayer in a second implantation window located within the first implantation window above the multilayer (8) and self-aligned with the emitter.

    MOS transistor production with gate length less than that imposed by photolithography comprises forming internal spacers in cavity arranged in pile before deposition of gate material
    5.
    发明专利
    MOS transistor production with gate length less than that imposed by photolithography comprises forming internal spacers in cavity arranged in pile before deposition of gate material 未知

    公开(公告)号：FR2823597A1

    公开(公告)日：2002-10-18

    申请号：FR0105013

    申请日：2001-04-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： SCHWARTZMANN THIERRY

    IPC: H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L29/78

    Abstract: The production of a MOS transistor comprises: (a) the formation, on a semiconductor substrate having a first type of conductivity, of a pile formed of a first semiconducting layer (1) having a second type of conductivity and a second insulating layer (2); (b) the definition by photolithography of a window engraved on the upper surface of the second insulating layer; (c) an engraving of the pile in the window to produce a cavity (3); (d) the formation in the cavity of an insulating region (4) supported on the sides of the cavity and having a transverse opening emerging on the upper surface of the substrate; (e) the formation on the upper surface of the substrate across the transverse opening of an oxide gate layer (6); (f) the deposition on the pile and in the transverse opening of a gate material layer (7); and (g) an engraving of the gate material layer and the pile, from one side to the other and at a distance from the edges of the insulating region, to form a block (BL) on the upper surface of the substrate. Independent claims are also included for the following: (a) a MOS transistor produced by the above process; and (b) an integrated circuit incorporating at least one MOS transistor of this type.

    Fabrication of metal oxide semiconductor transistor by producing gate and sacrificial block on substrate using single photolithographic mask, and producing drain extension by implantation of dopants
    10.
    发明专利
    Fabrication of metal oxide semiconductor transistor by producing gate and sacrificial block on substrate using single photolithographic mask, and producing drain extension by implantation of dopants 未知

    公开(公告)号：FR2826777A1

    公开(公告)日：2003-01-03

    申请号：FR0108677

    申请日：2001-06-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： SCHWARTZMANN THIERRY ,  JAOUEN HERVE

    IPC: H01L21/336 ,  H01L29/78

    Abstract: A metal oxide semiconductor (MOS) transistor is fabricated by producing a gate (GR) of transistor and a sacrificial block (BS) on a substrate (SB) using a single photolithographic mask. A drain extension (ZXT) is produced by specific implantation of dopants between the gate and the sacrificial block. The drain is produced by an implantation of dopants under the sacrificial block. Fabrication of an MOS transistor with a drain extension, comprises producing an implanted drain region on a substrate coated at a distance separating the gate which is greater tan the distance separating the gate from the implanted source region, and producing a drain extension zone lying in the substrate between a drain region and a gate. The gate of the transistor and a sacrificial block separated from the gate by a distance equal to the desired length for the drain extension, are produced on the upper surface of the substrate using a single photolithographic mask and the same gate material. The production of the drain extension comprises a specific implantation of dopants in the substrate between the gate and the sacrificial block. The production of the drain comprises an implantation of dopants in the sacrificial block located under the sacrificial block after removing the sacrificial block.

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