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    16.
    发明专利
    未知

    公开(公告)号：DE60023014D1

    公开(公告)日：2005-11-10

    申请号：DE60023014

    申请日：2000-11-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GALBIATI EZIO ,  NESSI MAURIZIO ,  SCHILLACI LUCA

    IPC: G11B21/08 ,  H02P25/034 ,  H02P7/00

    Abstract: The present invention concerns a circuit for the speed recovery of a direct current motor comprising an output stage (1), consisting of a first couple of transistors (MOS1, MOS2) and of a second couple of transistors (MOS3, MOS4), and first means (5) for detecting a current circulating (Ivcm) in said motor. The inventive circuit has the characteristic of. comprising second means (7) suitable for activating said second couple of transistors (MOS3, MOS4) of said output stage (1) for a determined first time period (Tbrk) so as to short-circuit said motor (2), and at the end of said first time period (Tbrk) said second means (7) being suitable for unbalancing said output stage (1) so as to force the maximum current circulating (Ivcm) for a determined second time period (Tact) in function of the value detected by said first means (5) during said first time period (Tbrk) so as to stop said motor (2) in the shortest time possible.

    17.
    发明专利
    未知

    公开(公告)号：DE69927373D1

    公开(公告)日：2005-10-27

    申请号：DE69927373

    申请日：1999-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GALBIATI EZIO ,  BOSCOLO MICHELE ,  VITI MARCO

    IPC: H02P6/182 ,  H02P6/18

    Abstract: A method of detecting the zero-cross event of an induced back electromotive force or of the nullification instant of a periodic current in a PWM driven winding, by circuits generating an analog signal representative of said back electromotive force or of said current, means for comparing said analog signal with zero and producing a first logic signal (READ _ZC), means for generating a PWM driving signal, means for storing the duration of the time interval between two consecutive zero-cross events, includes: storing the value (TC) of the time interval between the last two events of zero-cross detected; synchronizing the PWM driving signal at the end of a time interval from the instant of the last zero-cross detected of duration equal to the difference between ae time (TS) established in function of said stored value (TC) and a first prefixed value (T1); if a new zero-cross event is not detected within said established time (TS), disabling the switching of the PWM signal for a time interval, the maximum duration of which is equal to a second prefixed value or until the occurrence of a new zero-cross event. A hardware implementation is also described.

    19.
    发明专利
    未知

    公开(公告)号：DE69813843D1

    公开(公告)日：2003-05-28

    申请号：DE69813843

    申请日：1998-12-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GALBIATI EZIO ,  PAPILLO LORENZO ,  CHRAPPAN SOLDAVINI FRANCESCO

    IPC: G06F1/025 ,  H02M7/5387

    Abstract: In driving a load in a PWM mode in function of numeric command values of a certain N number of bits by converting the current numeric command value in at least a driving PWM signal (PWM_A, PWM_B) having a fixed frequency and a duty cycle proportional to the numeric command value, comparing through a comparator (COMPARATOR) the N bit numeric value with the counter of an up/down counter of the same number (N) of bits (N BIT UP/DOWN COUNTER) functioning in a continuous mode at the frequency of a system's clock signal (SysClk), the definition of the conversion may be enhanced withtout correspondingly increasing the number of bits of the UP/DOWN COUNTER. This is achieved by incrementing by more than a unit (N+3) the number of bits on which a certain command value is mapped; converting the N most significant bits with the exception of said additional bits of said command value by means of said comparator and up/down counter; decoding said additional bits by generating a corresponding plurality of intermediate levels of variation of the duty cycle, each of which has a duration of half a clock period (SysClk/2) producing a plurality of signals, outphased among each other by half a clock period (A, B, C, D, B, A', B', C', D', E'); generating said driving PWM signal (IN_A, IN_B) by multiplating (MULTIPLEXER) said signals outphased among each other by half a clock period, carrying out logic combinations of such signals in function of the most significative bit (MSB) of the numeric command value and of said least significative additional bits.

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