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公开(公告)号：JPH07263971A
公开(公告)日：1995-10-13
申请号：JP6682295
申请日：1995-02-28
Applicant: ST MICROELECTRONICS SRL
Inventor： CHRAPPAN FRANCESCO , NESSI MAURIZIO , SALINA ALBERTO
IPC: H03F3/20 , H02P25/034 , H03F1/32 , H03F3/30 , H03F3/347
Abstract: PURPOSE: To effectively control the operation of an externally connected output power transistor(TR) by directly driving it with the output of an operational amplifier without using any external sense resistance. CONSTITUTION: A buffer stage BF1 shifts its input voltage toward a ground potential by a value equal to the threshold voltage of M2 under a zero-input condition. Therefore, the gate-source voltage of the external power transistor TRM 4 which is driven by the buffer becomes zero under the zero-input condition and its turn-off state is secured. As the current which is led out by the load increases, the output voltage VOP1 of a signal amplifier OP1 increases and a TRM2 is placed nearly in its saturated state. Here, when the current that the load requires becomes larger than the limit current IM2 passing through the M2, a maximum current like this which passes through the M2 is limited by a resistance R, so the output voltage of the signal amplifier OP1 increases until it meets a condition of VBF1 >Vth M4 +V0 and an external power TR is turned off.
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公开(公告)号：JP2002186282A
公开(公告)日：2002-06-28
申请号：JP2001311377
申请日：2001-10-09
Applicant: ST MICROELECTRONICS SRL
Inventor： BRAMBILLA MASSIMILIANO , NESSI MAURIZIO
Abstract: PROBLEM TO BE SOLVED: To provide a drive circuit for voice coil motor that ensures high accuracy in the position of a read/write head in track following mode. SOLUTION: A control circuit is provided with a first and a second class AB amplifiers. The outputs of the class AB amplifiers are connected with a terminal of a first resistor in series with a voice coil motor so that current will be passed through the voice coil motor and the first resistor. The circuit is provided with a sense amplifier the input terminal of which is coupled with the terminal of the first resistor; and a device at the input of which there is a signal equivalent to the sum of an external signal and an output signal of the sense amplifier. The control circuit drives the first amplifier and the second amplifier in a phase inverted by an output signal generated by the above device. A second resistor is placed in series with the first resistor so that the above current will be passed through the first and the second resistors in series. The sense amplifier is provided with a means for including an input terminal coupled with the terminals of the resistors in series.
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公开(公告)号：JP2002223588A
公开(公告)日：2002-08-09
申请号：JP2001354965
申请日：2001-11-20
Applicant: ST MICROELECTRONICS SRL
Inventor： GALBIATI EZIO , NESSI MAURIZIO , SCHILLACI LUCA
IPC: G11B21/08 , H02P25/034 , H02P7/00
Abstract: PROBLEM TO BE SOLVED: To prevent collision of an arm for supporting a read and/or write head with the end of a stroke position of an inside or an outside of a platter having a hard disk. SOLUTION: A speed recovering circuit for a DC current motor comprises a second means 7, which is suitable to start a second set of transistors MOS3 and MOS4 of an output stage 1 during a first period Tbrk preset to short circuit the motor 2. In this case, the second means 7 is adapted, so as to set a maximum circulating current Ivcm during a prescribed second time period Tact of a function of the value detected by a first means 5 during the first time period Tbrk by setting an output stage 1 to an unbalanced state, when the first period Tbrk is finished and to stop the motor 2 in the shortest time possible.
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公开(公告)号：JPH11136099A
公开(公告)日：1999-05-21
申请号：JP24622998
申请日：1998-08-31
Applicant: ST MICROELECTRONICS SRL
Inventor： ROSSI ANNAMARIA , FUCILI GIONA , MARCELLO LEONE , NESSI MAURIZIO
Abstract: PROBLEM TO BE SOLVED: To produce an XOR gate with use of a small number of transistors TR by connecting the output terminal of a flip-flop corresponding to the output terminal Q of a D type flip-flop to the gate terminal of a prescribed TR and also to a circuit node in a feedback way. SOLUTION: Only three TRs are used in addition to a TR consisting of a reference inverted input stage that is driven by the reference timing signals fi and Nfi (having non-superimposed phases). An XNOR input stage includes two TR M1 and M2 which are connected in series between an input terminal T and an output circuit node A via the source and drain terminals respectively. The gate terminal of the 1st TR M1 is connected to a node C, and the signal Nfi is applied to the gate terminal of the 2nd TR M2. Then a 3rd TR M3 is connected between a circuit power line Vdd and a circuit node B.
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公开(公告)号：JPH07107773A
公开(公告)日：1995-04-21
申请号：JP14242594
申请日：1994-05-31
Applicant: ST MICROELECTRONICS SRL
Inventor： NESSI MAURIZIO
IPC: H02P6/08 , H03K17/042 , H03K17/16
Abstract: PURPOSE: To provide a comparator circuit, capable of resolving disadvantages that a conventional slew rate control circuit often generates a delay in the switching of a turn-off and actual use is limited, and suppressing the delay of the turn-off to a minimum which corresponds to the change of load conditions. CONSTITUTION: This circuit is provided with a comparator (M2+I2), capable of forming signals which are the displays, when an output power transistor MP reaches saturation or deviates from it, and a logic AND gate AN1 to be supplied with the signals and a discharge switch M1 which is switched by the signals.
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Patent Agency Ranking
公开(公告)号：JPH0792279A
公开(公告)日：1995-04-07
申请号：JP5921594
申请日：1994-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： FUCILI GIONA , NESSI MAURIZIO
Abstract: PURPOSE: To provide a generator of programmable time interval by which the accuracy can be improved in comparison with a conventional digital generator. CONSTITUTION: The time interval generating device comprises the first and second digital counters 1, 5 a memory 2, a digital divider 3, and a digital adding machine 4, the counting is started by the counter 1 when the first event is generated, then only. the digit of higher position of a figure of the counted number, is memorized when the second event is generated, thereby the dividing by the omission, is performed. At least two separate fractions are obtained from the memorized number by the divider 3, and the fractions are added by the adding machine 4 operated in the binary digit string. The counter 5 counts down the sum to generate a signal at the clearing.
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公开(公告)号：DE60023014D1
公开(公告)日：2005-11-10
申请号：DE60023014
申请日：2000-11-20
Applicant: ST MICROELECTRONICS SRL
Inventor： GALBIATI EZIO , NESSI MAURIZIO , SCHILLACI LUCA
IPC: G11B21/08 , H02P25/034 , H02P7/00
Abstract: The present invention concerns a circuit for the speed recovery of a direct current motor comprising an output stage (1), consisting of a first couple of transistors (MOS1, MOS2) and of a second couple of transistors (MOS3, MOS4), and first means (5) for detecting a current circulating (Ivcm) in said motor. The inventive circuit has the characteristic of. comprising second means (7) suitable for activating said second couple of transistors (MOS3, MOS4) of said output stage (1) for a determined first time period (Tbrk) so as to short-circuit said motor (2), and at the end of said first time period (Tbrk) said second means (7) being suitable for unbalancing said output stage (1) so as to force the maximum current circulating (Ivcm) for a determined second time period (Tact) in function of the value detected by said first means (5) during said first time period (Tbrk) so as to stop said motor (2) in the shortest time possible.
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公开(公告)号：DE69414820T2
公开(公告)日：1999-04-15
申请号：DE69414820
申请日：1994-02-28
Applicant: ST MICROELECTRONICS SRL
Inventor： CHRAPPAN FRANCESCO , NESSI MAURIZIO , SALINA ALBERTO
IPC: H03F3/20 , H02P25/034 , H03F1/32 , H03F3/30 , H03F3/347
Abstract: The operation of externally connected output power transistors of a class AB amplifier is controlled without employing any external sensing resistance of the output current by driving an externally connected power transistor through a level shifting buffer and employing a limiting network composed of an integrated transistor driven by the output of a signal amplifying stage and a resistance connected in series with its drain. The buffer stage shifts the level of the driving signal of the external power transistor by a value equal to the threshold voltage of the integrated transistor of the limiting network thus ensuring the turn-off of the external power transistor under quiescent conditions.
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公开(公告)号：DE69507126D1
公开(公告)日：1999-02-18
申请号：DE69507126
申请日：1995-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： FUCILI GIONA , NESSI MAURIZIO
Abstract: Masking of switching noise is implemented in the driving system of an "H" bridge stage by exploiting the periodic signal generated by a PWM control circuit (normally present in the control system for controlling the "H" bridge in an open-loop mode) for masking the decay time of the disturbances caused by the switching from off-to-on of a first pair of switches of the bridge that drive a current in a certain direction through the load. This is implemented by keeping high for a preset period of time the periodic signal generated by the PWM circuit and varying the duty-cycle of the signal for regulating the mask time in function of the load characteristics. The system further comprises the masking of the decay interval of the disturbances caused by the switching from on-to-off of the first pair of switches and from off-to-on of the other pair of switches that provide a current ricirculation path of the energy stored in the reactance of the load, for a preset number of clock cycles, thus impeding any subsequent switching for the duration of this second mask. This second mask may be realised in different ways. The use of an up-counter and a programmable comparator been preferred.
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公开(公告)号：ITMI20081632A1
公开(公告)日：2010-03-13
申请号：ITMI20081632
申请日：2008-09-12
Applicant: ST MICROELECTRONICS SRL
Inventor： NESSI MAURIZIO , SCHILLACI LUCA
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