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    11.
    发明专利
    未知

    公开(公告)号：DE602004009779T2

    公开(公告)日：2008-08-28

    申请号：DE602004009779

    申请日：2004-07-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARINO FILIPPO ,  CANNELLA ELIANA

    IPC: H03M1/20 ,  H02M3/157 ,  H03M1/48

    Abstract: An apparatus adapted to convert an input analog signal (In) to an output digital signal (OUT) is described. The apparatus comprises means (1) adapted to convert a first digital value (d(IN1)) of the output signal of the apparatus (100) to a first analog value (IN1), said first digital value (d(IN1)) being emitted by the apparatus at a first time instant, and means for feeding back the first analog value (IN1) to the input of the apparatus. The apparatus (100) comprises first means (2, 3) adapted to determine the difference (Diff) between the first analog value (IN1) and a second analog value (IN) of the input signal of the apparatus at a second time instant successive to the first time instant, second means (4) adapted to convert said difference (Diff) to a digital value (d(Diff)) and third means (5) adapted to add or subtract said digital value (d(Diff)) of said difference to or from said first digital value (d(IN1)) by obtaining said output digital signal (OUT).

    12.
    发明专利
    未知

    公开(公告)号：DE69830469D1

    公开(公告)日：2005-07-14

    申请号：DE69830469

    申请日：1998-03-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARINO FILIPPO

    IPC: G05F1/618 ,  G05F3/20

    Abstract: A control circuit comprising a plurality of input terminals (HSTRAP,HSRC) and at least one output terminal (POLEPI) for biasing a floating well (EPI) in a semiconductor integrated circuit structure, and comprising a first transistor (NCH1) which has its conduction terminals connected between a first input terminal (HSTRAP) and an output terminal (POLEPI), and a second transistor (PCH1) which has its conduction terminals connected between a second input terminal (HSTRAP) and the output terminal (POLEPI), wherein the output terminal (POLEPI) is coupled to each of the control terminals of said first and second transistors through a regulator (Dz).

    15.
    发明专利
    未知

    公开(公告)号：IT1308062B1

    公开(公告)日：2001-11-29

    申请号：ITTO990453

    申请日：1999-05-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARINO FILIPPO

    IPC: H02M1/00 ,  H02M1/32

    Abstract: The method of a protection circuit includes a reference voltage source and at least one circuit which are connected together via a switch. A memory element is connected to the input of the circuit, downstream of the switch. The switch is temporarily opened by a control signal generated by a monostable circuit when detecting switching of power elements belonging to an electronic device embedding the protection circuit. When the switch is open, the memory element supplies the circuit with the reference voltage previously stored. In this way, switching of the power element that might cause noise on the reference voltage cannot disturb the circuit and thereby cannot cause a faulty operation of the latter.

    17.
    发明专利
    未知

    公开(公告)号：ITTO991148D0

    公开(公告)日：1999-12-23

    申请号：ITTO991148

    申请日：1999-12-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARINO FILIPPO ,  CAPICI SALVATORE

    IPC: G01R31/28 ,  H01L23/495

    Abstract: A method of making and testing an electronic device that includes providing first and second external pins, first and second pads on the substrate connected to the first external pin by respective bonding wires, and third and fourth pads on the substrate connected to the second external pin respective bonding wires, and to a first common line by respective resistors. With a circuit configuration of this type, the intactness of the bonding wires can easily be checked by carrying out a simple resistance measurement between the first and the second external pin.

    19.
    发明专利
    未知

    公开(公告)号：DE602005019590D1

    公开(公告)日：2010-04-08

    申请号：DE602005019590

    申请日：2005-12-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CANNELLA ELIANA ,  ADRAGNA CLAUDIO ,  MARINO FILIPPO ,  TUMMINARO SALVATORE

    IPC: H02M1/38 ,  H02M3/337

    Abstract: Described herein is a device for driving a converter circuit that supplies a charge via a first electronic switch (LS) and a second electronic switch (HS) alternately turned on and off, with a first dead-time interval between turning-off of the first electronic switch and turning-on of the second electronic switch (HS) and a second dead-time interval between turning-off of the second electronic switch (HS) and turning-on of the first electronic switch. Turning-off of the second electronic switch (HS) is controlled as a function of a feedback signal (F) coming from the load (L). The device comprises: - a generator module (11a, C) for generating a memory signal (V c ), indicating the duration of the first dead-time interval; and - a delay module (11b, C, 14, 18, 20), sensitive to said memory signal (V c ) for controlling turning-on of the first electronic switch with a delay, with respect to turning-off of the second electronic switch (HS), identified by the aforesaid memory signal (V C ), so that the second dead-time interval has a duration substantially equal to the duration of the first dead-time interval.

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