公开(公告)号：DE60037504D1

公开(公告)日：2008-01-31

申请号：DE60037504

申请日：2000-05-31

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO ,  MONTANARO MASSIMO ,  ODDONE GIORGIO

IPC: G11C16/28 ,  G11C11/56

Abstract: The invention relates to a circuit structure (1) for reading data contained in an electrically programmable/erasable integrated non-volatile memory device, comprising a matrix (2) of memory cells (3) and at least one reference cell (4) for comparison with a memory cell (3) during a reading phase. The reference cell (4) is incorporated in a reference cells sub-matrix (5) which is structurally independent of the matrix (2) of memory cells (3). Also provided is a conduction path between the matrix (2) and the sub-matrix (5), which path includes bit lines (b1ref) of the submatrix (5) of reference cells (4) extended continuously into the matrix (2) of memory cells (3)

公开(公告)号：ITMI20031619A1

公开(公告)日：2005-02-07

申请号：ITMI20031619

申请日：2003-08-06

Applicant: ST MICROELECTRONICS SRL

Inventor： MONTANARO MASSIMO ,  PAGLIATO MAURO ,  ROLANDI PAOLO

IPC: G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  H01L20060101

公开(公告)号：DE69632023D1

公开(公告)日：2004-05-06

申请号：DE69632023

申请日：1996-01-31

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO ,  MONTANARO MASSIMO

IPC: G01R19/165 ,  H03K17/30 ,  H03K17/00

Abstract: The circuit, in accordance with the present invention for detecting the presence at a signal input (IT) of a high voltage higher than a predetermined value and signaling it to a signal output (OT) through a logical type signal comprises one or more first transistors (P1-...) of type MOS and of a predetermined conductivity type each diode-connected and having its body terminal connected to the source terminal and having principal conduction paths connected in series for current conduction between a first node (ND1) and a ground input (GND) and two or more second transistors (P2-...) of the MOS type and of the same conductivity type each one diode-connected and having its body terminal connected to the source terminal and having principal conduction paths connected in series for current conduction between the signal input (IT) and the first node (ND1) and at least one first logical inverter (M1,M2) of the CMOS type having its input connected to the first node (ND1) and its output coupled to the signal output (OT) and connected for power supply to a power supply input (VDD) and to the ground input (GND).