公开(公告)号：JPH0855496A

公开(公告)日：1996-02-27

申请号：JP7308495

申请日：1995-03-30

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO

IPC: G11C29/00 ,  G11C14/00 ,  G11C16/04 ,  G11C16/26 ,  G11C29/04

Abstract: PURPOSE: To eliminate the need for a reset circuit by connecting a 1st and a 2nd memory cell to a write circuit during writing and to a bistable circuit during reading by a switching circuit element. CONSTITUTION: During a test, a connection with the write circuit WRT is made by switching circuits SW1 and SW2 of electronic or complementary transistors to perform a writing process. During this operation, elements WS1 and WS2 enable only a reading process instead of a connection with a memory cell to store storage information in a flip-flop type circuit LATCH. During the writing process, one cell is written and the other cell is cleared. When the device turns on, the elements SW1 and SW2 enters a direct operation state in response to actuation to the circuit LATCH and there is no power consumption. When one memory cell is written to a logical high level in response to the said turning-on operation, the circuit LATCH enters a prescribed state. The circuit LATCH which is made unbalanced by the cell where the information is written holds the other cell in the cleared state each time the power source is turned on.

公开(公告)号：JP2000137999A

公开(公告)日：2000-05-16

申请号：JP30499899

申请日：1999-10-27

Applicant: ST MICROELECTRONICS SRL

Inventor： RIVA MARCO ,  ROLANDI PAOLO ,  MONTANARO MASSIMO

IPC: G06F12/16 ,  G11C11/56 ,  G11C16/02 ,  G11C29/12 ,  G11C29/50 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To replace a damaged cell by reading each memory cell constituting a storage device, comparing each memory cell with at least one reference memory cell at one time, determining whether the threshold of the memory cell is smaller than that of at least one reference memory cell, and determining the number of memory cells each having threshold larger than that of at least one reference cell. SOLUTION: A memory cell 10 checks a barging state, and a column multiplexer 11 selects a memory cell 10 belonging to a memory matrix allocated line. Reference memory cells 12:12a to 12f respectively have gradually increasing thresholds, and indicate reference memory cells connected to corresponding sense amplifying means 15. The output of each of the sense amplifying means 15 is connected to an encoder means 16, and the encoder means 16 is adapted to encode a result before the number of memory cells having thresholds exceeding those of the reference memory cells is counted.

公开(公告)号：JP2001014875A

公开(公告)日：2001-01-19

申请号：JP2000182753

申请日：2000-06-19

Applicant: ST MICROELECTRONICS SRL

Inventor： BARCELLA ANTONIO ,  ROLANDI PAOLO

IPC: G11C16/02 ,  G11C16/06 ,  G11C16/28

Abstract: PROBLEM TO BE SOLVED: To realize a read-out system for a memory cell the detection ratio of which depends on read-out voltage. SOLUTION: This method has a first process in which a memory cell 2 of a memory matrix 3 is selected by a row decoder 5 and a column multiplexer 4, a second process in which voltage on a drain electrode of a selected memory cell P2 is pre-loaded so as to reach a previously prescribed value and equalization processing is performed, and a third process in which a selected memory cell P2 is read out with a detection ratio depending on read-out voltage of this memory cell.

公开(公告)号：JP2000057788A

公开(公告)日：2000-02-25

申请号：JP14091799

申请日：1999-05-21

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO

IPC: G11C16/02 ,  G11C11/00 ,  G11C11/56

Abstract: PROBLEM TO BE SOLVED: To provide a high memory-capacity nonvolatile memory device of a high reliability. SOLUTION: This is a memory device having a memory cell array 1 including at least one memory block B0-B7 equipped with a plurality of multilevel memory cells constituted to store information of N>=2 bits. At least one memory block B0-B7 includes a plurality of electrically erasable programmable bilevel memory cells each constituted to store 1-bit information, and read means 2, 5, 3 which access and read one multilevel memory cell or, access and read simultaneously N electrically erasable programmable bilevel memory cells depending on an address signal A0-A21 supplied to the memory device.

公开(公告)号：JPH05102825A

公开(公告)日：1993-04-23

申请号：JP12301991

申请日：1991-04-26

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO ,  MACCALLI MARCO ,  DALLABORA MARCO

IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175

Abstract: PURPOSE: To reduce noise at an output terminal by lowering a peak current at the time of switching operation in a CMOS logic circuit being a buffer-type data output stage having a 1st feedback loop and a 2nd feedback loop. CONSTITUTION: This buffer-type data output stage CMOS logic circuit is composed of the 1st and the 2nd feedback loops 8 and 9 having a mutually independent configuration respectively, connected between a common output node 3 and each gate electrode of corresponding transistors M1 and M2, and precharging the output node 3 at a prescribed voltage value. The 1st feedback loop 8 is operated in a logic H of the output node 3, and the 2nd feedback loop 9 is operated at the time of a logic L, to precharge the output node 3, the peak current in a switching period is lowered, and the noise in the switching period is reduced.

公开(公告)号：JP2003123486A

公开(公告)日：2003-04-25

申请号：JP2002287067

申请日：2002-09-30

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO

IPC: G11C16/02 ,  G11C11/56 ,  G11C19/28

Abstract: PROBLEM TO BE SOLVED: To enable increasing capacity of a storage device of a nonvolatile memory. SOLUTION: In a programming method of a multi-level, each memory region can be programmed by non-binary-number of a level, and integer of bits, for example 5, is stored in an adjacent memory region. Therefore, bits to be stored in two memory regions are divided into two sets, a first set prescribes a level of binary number being higher than a level of non-binary number. When the first set written during programming corresponds to a level being lower than a level of non-binary number, the first set is written in the first region and the second set is written in the second region (33, 34). When it is higher than non-binary number of a level, the first set is written in the second region and the second set is written in the first region (35, 36). The first set written in the second region is stored with a level being different from the second set. Consequently, writing of a level stored in the first set is confirmed, and bits read out from two regions are almost related to bits of two sets.

公开(公告)号：JPH08306190A

公开(公告)日：1996-11-22

申请号：JP22355395

申请日：1995-08-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CALLIGARO CRISTIANO ,  GASTALDI ROBERTO ,  ROLANDI PAOLO ,  TORELLI GUIDO

IPC: G11C11/419 ,  G11C7/06

Abstract: PROBLEM TO BE SOLVED: To obtain a readout circuit which is used for a memory having a differential cell, and which can be used even in memory reading by a reference cell technique and improves a data read speed and low voltage operations. SOLUTION: A readout circuit has two leg parts SX, DX which are connected to between power source terminals Vdd and Vss , and each of the leg parts series- connects an electronic switch SW1 or SW2; a passive element T1 or T2 forming a voltage amplifier which is feedback-connected to a passive element T2 or T1 in another leg part; and a switch load element L1 or L2 to each other. Each of the passive elements is driven via a high impedance circuit element D1 or D2.

公开(公告)号：EP0455002B1

公开(公告)日：1997-12-29

申请号：EP91105323

申请日：1991-04-04

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO ,  MACCALLI MARCO ,  DALLABORA MARCO

IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175

CPC classification number: H03K19/00361

公开(公告)号：DE602005019069D1

公开(公告)日：2010-03-11

申请号：DE602005019069

申请日：2005-11-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO

IPC: G11C8/06 ,  G11C16/04 ,  G11C16/08

Abstract: The invention relates to a method for accessing, in reading, programming and/or erasing, to a semiconductor integrated non volatile memory device of the Flash EEPROM type with a NAND architecture comprising at least one memory matrix (2) organised in rows or word lines (WL) and columns or bit lines (BL), and wherein, for the memory, a plurality of additional address pins are provided. Advantageously, the method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with said additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to said additional address pins are also provided to allow a double addressing mode, sequential and in parallel.

公开(公告)号：DE602005003788T2

公开(公告)日：2010-01-28

申请号：DE602005003788

申请日：2005-04-11

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO

IPC: G11C16/16