公开(公告)号：ITVA20070060A1

公开(公告)日：2009-01-05

申请号：ITVA20070060

申请日：2007-07-04

Applicant: ST MICROELECTRONICS SRL

Inventor： ALESSANDRO AGATINO ANTONINO ,  RIBELLINO CALOGERO

公开(公告)号：DE60035113T2

公开(公告)日：2008-02-07

申请号：DE60035113

申请日：2000-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： SIGNORELLI TIZIANA ,  PULVIRENTI FRANCESCO ,  RIBELLINO CALOGERO

IPC: G01R31/30 ,  G06F11/00

Abstract: The invention relates to a circuit architecture and a relevant method for performing a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices. The circuit architecture of this invention comprises at least one non-volatile memory unit (3) having non-volatile memory elements (5) and a means (17,19) for modifying the state of the memory elements (5), a first multifunctional input pin (8) whereon a sequence (25) of trimming data is received, a second multifunctional input pin (9) whereon a timing signal of the trimming operations is received, and an additional access pin (7) for switching the circuit architecture operation from the normal mode over to the trimming mode. This circuit architecture further comprises a volatile memory unit (2) associated with the non-volatile memory unit (3) for storing up the non-volatile memory (3) state at power-on or at the simulating phase, and storing up the sequence (25) of trimming data at the programming phase; an interface (6) is provided between said pins (7,8,9) and the memory unit (2,3) for initially storing the data sequence (25) into the volatile memory unit and subsequently timing the trimming operation.

公开(公告)号：DE60035113D1

公开(公告)日：2007-07-19

申请号：DE60035113

申请日：2000-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： SIGNORELLI TIZIANA ,  PULVIRENTI FRANCESCO ,  RIBELLINO CALOGERO

IPC: G01R31/30 ,  G06F11/00

Abstract: The invention relates to a circuit architecture and a relevant method for performing a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices. The circuit architecture of this invention comprises at least one non-volatile memory unit (3) having non-volatile memory elements (5) and a means (17,19) for modifying the state of the memory elements (5), a first multifunctional input pin (8) whereon a sequence (25) of trimming data is received, a second multifunctional input pin (9) whereon a timing signal of the trimming operations is received, and an additional access pin (7) for switching the circuit architecture operation from the normal mode over to the trimming mode. This circuit architecture further comprises a volatile memory unit (2) associated with the non-volatile memory unit (3) for storing up the non-volatile memory (3) state at power-on or at the simulating phase, and storing up the sequence (25) of trimming data at the programming phase; an interface (6) is provided between said pins (7,8,9) and the memory unit (2,3) for initially storing the data sequence (25) into the volatile memory unit and subsequently timing the trimming operation.

公开(公告)号：ITMI992250A1

公开(公告)日：2001-04-28

申请号：ITMI992250

申请日：1999-10-28

Applicant: ST MICROELECTRONICS SRL

Inventor： RIBELLINO CALOGERO ,  MILAZZO PATRIZIA ,  PULVIRENTI FRANCESCO

IPC: H02J7/00

Abstract: A control circuit for controlling current of batteries at the end of the charging phase, especially for lithium batteries, including an input/output circuit, placed between a battery charger and a battery, and an output stage, including two transistors, wherein the resistance of one of the two transistors is modulated to increase the value of the total resistance and to cause a lower turning off current of said output stage.