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    CONTROL CIRCUIT OF ZERO-BIAS CURRENT LOW-SIDE DRIVER
    2.
    发明专利
    CONTROL CIRCUIT OF ZERO-BIAS CURRENT LOW-SIDE DRIVER 失效

    公开(公告)号：JPH0722851A

    公开(公告)日：1995-01-24

    申请号：JP9588194

    申请日：1994-04-09

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： MILAZZO PATRIZIA ,  BONTEMPO GREGORIO ,  ALZATI ANGELO

    IPC: H03F1/02 ,  H02M1/08 ,  H03F3/21 ,  H03K17/00 ,  H03K17/0412 ,  H03K17/687

    Abstract: PURPOSE: To turn steady current consumption to zero without losing characteristics by providing a control circuit with a switch for blocking a current from a discharge current oscillator having control node capacitance when a power transistor(TR) is in an OFF state. CONSTITUTION: When a power TR PW is in an OFF state, the gate voltage of a TR M5 is also reduced. In the case of a switch OFF phase, the resistance of the TR M5 is increased and mismatch between currents I1, I2 is generated. The generation of a mis-matching trouble can be removed by determining the dimensions of the TR M5 so that large mismatch is generated when the power TR PW is slipped out of the saturation. Thereby the TR M5 operates as a switch to be opened when the gate voltage of the power TR PW is dropped less than the threshold voltage of the TR M5 and turns off a branch I2. Consequently the speed characteristics of the current oscillator I2 and the switch M5 can be held.

    4.
    发明专利
    未知

    公开(公告)号：DE69732695D1

    公开(公告)日：2005-04-14

    申请号：DE69732695

    申请日：1997-07-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PULVIRENTI FRANCESCO ,  MILAZZO PATRIZIA

    IPC: G05F1/565

    Abstract: A linear type of voltage regulator, having at least one input terminal (VBAT) adapted to receive a supply voltage and one output terminal (VOUT) adapted to deliver a regulated output voltage, comprises a power transistor (M1) and a driver circuit for the transistor; the driver circuit comprises essentially an operational amplifier (OP1) having an input differential stage biased by a bias current which varies proportionally with the variations of the regulated output voltage at the output terminal (VOUT) of the regulator.

    5.
    发明专利
    未知

    公开(公告)号：DE69808950D1

    公开(公告)日：2002-11-28

    申请号：DE69808950

    申请日：1998-12-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RIBELLINO CALOGERO ,  MILAZZO PATRIZIA ,  PULVIRENTI FRANCESCO

    IPC: H03K4/02 ,  H03K17/16

    Abstract: Integrated circuit (20, 80, 90) generating at least a voltage linear ramp having a slow rise of the type comprising an input terminal (21, 81, 91), connected to a first voltage reference (VREF) and an output terminal (24, 84, 94) adapted for providing a controlled ramp signal (VRAMP), the circuit comprising at least one operational amplifier (OP3) having a non-inverting input terminal connected to said input terminal (21, 81, 91) and to an output terminal in feedback on an inverting input terminal and connected to the output terminal (24, 84, 94) of the ramp generator circuit (20, 80, 90) itself. The ramp voltage generator (20, 80, 90) according to the invention further comprises a first storage capacitance (Cs) connected between the non-inverting input terminal of the operational amplifier (OP3) and a ground voltage reference (GND) and loaded by means of a second pumping capacitance (Cp) inserted in parallel to said first capacitance (Cs) between the input terminal (21, 81, 91) of the ramp generator circuit (20, 80, 90) and the ground voltage reference (GND).

    6.
    发明专利
    未知

    公开(公告)号：DE60315614D1

    公开(公告)日：2007-09-27

    申请号：DE60315614

    申请日：2003-06-18

    Applicant: ST MICROELECTRONICS DES & APPL ,  ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

    Inventor： CHESNAU DAVID ,  MERCANDANTE GIACOMO ,  MILAZZO PATRIZIA ,  BERNARD CHRISTOPHER

    IPC: H02J7/00 ,  H02M1/08

    Abstract: A circuit (225) for controlling a battery-charger device (200) with a closed-loop architecture is proposed. The circuit includes sensing means (230) for sensing an operative quantity of the device, means (245) for alternately controlling the sensing means to track the operative quantity during a tracking phase and to hold the operative quantity during a holding phase, and driving means (240) for providing a regulation signal, for regulating the operative quantity, according to a comparison between the sensed operative quantity and a reference value; the circuit of the invention further includes means (245;485-490) for causing the driving means to hold the regulation signal during at least part of each holding phase.

    7.
    发明专利
    未知

    公开(公告)号：DE69825755D1

    公开(公告)日：2004-09-23

    申请号：DE69825755

    申请日：1998-10-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RIBELLINO CALOGERO ,  MILAZZO PATRIZIA

    IPC: H03K19/0185

    Abstract: The invention relates to a level shifter electronic device with very low consumption of current, of the type supplied between a first voltage reference (VOUT) of power supply and a second voltage reference (GND) and comprising a circuital portion (2) with differential cell having an output terminal (OUT) and at least a first (4) and a second (5) input terminal, on the output terminal a signal translated in level with respect to the signal present on one (4) of said input terminals, being drawn. The device further comprises an additional circuital portion (3) connected to a node (A) of the differential cell and comprising at least a pull-down component (9) inserted between said node and the second voltage reference (GND). The pull-down component (9) is a MOS transistor (M6) having the conduction terminals connected between said node (A) and the second voltage reference (GND) and the gate terminal connected to the first voltage reference (VOUT) of power supply by means of a series of transistors.

    8.
    发明专利
    未知

    公开(公告)号：DE69808950T2

    公开(公告)日：2003-12-24

    申请号：DE69808950

    申请日：1998-12-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RIBELLINO CALOGERO ,  MILAZZO PATRIZIA ,  PULVIRENTI FRANCESCO

    IPC: H03K4/02 ,  H03K17/16

    Abstract: Integrated circuit (20, 80, 90) generating at least a voltage linear ramp having a slow rise of the type comprising an input terminal (21, 81, 91), connected to a first voltage reference (VREF) and an output terminal (24, 84, 94) adapted for providing a controlled ramp signal (VRAMP), the circuit comprising at least one operational amplifier (OP3) having a non-inverting input terminal connected to said input terminal (21, 81, 91) and to an output terminal in feedback on an inverting input terminal and connected to the output terminal (24, 84, 94) of the ramp generator circuit (20, 80, 90) itself. The ramp voltage generator (20, 80, 90) according to the invention further comprises a first storage capacitance (Cs) connected between the non-inverting input terminal of the operational amplifier (OP3) and a ground voltage reference (GND) and loaded by means of a second pumping capacitance (Cp) inserted in parallel to said first capacitance (Cs) between the input terminal (21, 81, 91) of the ramp generator circuit (20, 80, 90) and the ground voltage reference (GND).

    9.
    发明专利
    未知

    公开(公告)号：ITTO990995A1

    公开(公告)日：2001-05-16

    申请号：ITTO990995

    申请日：1999-11-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RIBELLINO CALOGERO ,  MILAZZO PATRIZIA

    IPC: H02M1/00 ,  H02M1/36

    Abstract: A switch-type regulator with a soft-start function having an output terminal supplying an output voltage, and including an error amplifier, having a first input receiving a constant reference voltage, a second input receiving a feedback voltage dependent on the output voltage, and supplying a compensation terminal with an error voltage correlated to the difference between the reference voltage and the feedback voltage. The error amplifier includes a differential amplifier. The regulator also includes a compensation network connected to the compensation terminal. A soft-start function is obtained exploiting the compensation network.

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