公开(公告)号：EP1657925A1

公开(公告)日：2006-05-17

申请号：EP06075049.4

申请日：2003-08-15

Applicant: STMicroelectronics Limited

Inventor： Dellow, Andrew ,  Bennett, Peter

IPC: H04N7/16 ,  G06F12/14

CPC classification number: G06F12/1483 ,  H04N21/443 ,  H04N21/4623

Abstract: Data is retrieved from a data memory by transmitting instructions containing the memory address of the data to be retrieved. A privileged data table stores a list identifying those regions of the data memory that store privileged or sensitive data. A privileged rule enforcer determines whether an instruction is attempting to access privileged data by comparing the address contained in the instruction with the regions of memory identified by the privileged data table as storing privileged data. If the instruction is attempting to access privileged data, the privileged rule enforcer blocks the instruction, and therefore the data access, unless the instruction is identified as having been verified by a code verifier and the data access satisfies one or more data access rules. To determine whether an instruction has been verified, the privilege rule enforcer receives a privilege signal which is asserted when a verified instruction is transmitted. The data access rules are defined by a rule signal received by the privileged rule enforcer.

Abstract translation: 通过发送包含要检索的数据的存储器地址的指令从数据存储器检索数据。 特权数据表存储标识存储特权或敏感数据的数据存储器区域的列表。 特权规则执行者通过将指令中包含的地址与由特权数据表识别的存储器区域作为存储特权数据进行比较来确定指令是否尝试访问特权数据。 如果指令尝试访问特权数据，则特权规则执行者将阻止该指令，并因此阻止该数据访问，除非该指令被识别为已由代码验证器验证并且该数据访问满足一个或多个数据访问规则。 为了确定是否已经验证了指令，特权规则执行器接收到当发送已验证指令时被断言的特权信号。 数据访问规则由特权规则执行者接收的规则信号定义。

公开(公告)号：EP1578053A1

公开(公告)日：2005-09-21

申请号：EP04251573.4

申请日：2004-03-18

Applicant: STMicroelectronics Limited

Inventor： Dellow, Andrew ,  Cordero, Rodrigo

IPC: H04L9/18 ,  H04L9/06

CPC classification number: H04L9/0662 ,  H04L2209/04 ,  H04L2209/12

Abstract: A portion of data is obfuscated by performing a bitwise XOR function between the bits of the data portion and the bits of an associated mask. A mask used to obfuscate a data portion is generated as a function of the memory address of the data portion. A bitfield representing the memory address of the data portion is split into a plurality of subset bitfields. Each subset then forms the input of a corresponding primary randomising unit. Each primary randomising unit is arranged to generate an output bitfield that appears to be randomly correlated with the input, but which may be precisely determined from the input if certain secret information is known. Each primary randomising unit is also arranged so that a distinct output is generated for each distinct input. The output of the primary randomising units form the input into a series of secondary randomising units. Each secondary randomising unit is arranged to receive as an input at least one bit of the output of every primary randomising unit. The secondary randomising units are arranged to generate an output bitfield in a similar manner to the primary randomising units. The output of the secondary randomising units are then combined by concatenation to form a data mask. In one embodiment, each randomising unit comprises a look-up table whose contents are formed by permuting a sequence of ordered integers in a random manner. In this embodiment, the secret information corresponds to the contents of the look-up table. A mask is thus generated from the memory address of a data portion such that a distinct mask is generated for each distinct memory address, and such that there is a quasi-random correlation between the memory address and the corresponding mask.

公开(公告)号：EP1578051A1

公开(公告)日：2005-09-21

申请号：EP04251574.2

申请日：2004-03-18

Applicant: STMicroelectronics Limited

Inventor： Dellow, Andrew ,  Bennett, Peter ,  Cordero, Rodrigo

IPC: H04L9/00 ,  G06F12/14 ,  H04H1/00

CPC classification number: H04N7/162 ,  G06F12/1408 ,  H04H60/23 ,  H04N7/1675

Abstract: In an embodiment of the invention, a memory is provided to store data in an encrypted form. A modifiable register is arranged to store a memory address, a 0 , defining a boundary separating the memory into two regions. The lower region stores data encrypted using a key B, and the upper region stores data encrypted using a different key A. Data stored on the boundary address is encrypted using key A. Accordingly, when data is read from a memory address a, key A is used to decrypt the data if a≥a 0 , and key B is used if a 0 . However, when data is written to a memory address a, then key A is used to encrypt the data if a≥a 0 +1, key B is used if a 0 +1. The value of a 0 is then incremented by one. When data is written to the boundary address, a 0 , the position of the boundary is thus caused to increase by one unit. Initially, the value of a 0 is set to zero so that all data within the memory is encrypted using key A. As data is written to the memory, particularly on the boundary address, the value of a 0 gradually increases. Eventually the value of a 0 will exceed the highest address of the memory. At this point, all data within the memory is encrypted using key B, and a new key is generated. The new key becomes key B, and key A takes the value of the old key B. The value of a 0 is then set back to zero and the process is repeated. If a particular region of the memory is never written to, the value of a 0 will not increase beyond the lowest memory address of this region. To prevent this occurrence, if the value of a 0 does not change within a predetermined period of time then a 'kicker' process is activated. During the kicker process, data is caused to be read from the memory address a 0 , and then to be written back to the same location, thereby artificially stimulating an increase of the value of a 0 .

公开(公告)号：EP1544704A1

公开(公告)日：2005-06-22

申请号：EP03258079.7

申请日：2003-12-19

Applicant: STMicroelectronics Limited

Inventor： Dellow, Andrew ,  Gurney, Howard

IPC: G06F1/00

CPC classification number: G06F21/72 ,  G06F12/1408 ,  G06F21/79 ,  G06F21/85

Abstract: A monolithic semiconductor integrated circuit is provided for selectively encrypting or decrypting data transmitted between one of a plurality of devices on the circuit and an external memory. Two series of data pathways connect the devices and the external memory. The first series of data pathways passes through a cryptographic circuit causing data to be encrypted or decrypted, and the other series of data pathways provides an unhindered route. When a data access request is made by a device, the data is selectively routed along one of the two series of data pathways according to the identification of the device making the data access request. In one example, if data is transmitted from a device to the external memory, the data is selectively encrypted before being stored in the external memory if the device transmitting the data is identified as secure. Then, when that data is retrieved from the external memory by a second device, the data is selectively decrypted only if the second device is identified as secure.

Abstract translation: 一种单片半导体集成电路提供了一种用于选择性地加密或解密电路上的设备中的多个之一之间和外部存储器中的数据的反式mitted。 两个系列的数据通路的连接的装置和外部存储器中。 所述第一系列数据通路的经过加密电路使得数据被加密或解密，并且其他系列数据通路上不受阻碍的路径提供。 当一个数据访问请求是由设备做出，该数据被沿着两个系列gemäß到使数据访问请求的装置的识别数据通路中的一个选择性地路由。 在一个实施例中，如果数据是从一个装置到外部存储器反式mitted，数据被选择性地存储在外部存储器如果发射数据的设备被识别为安全的之前被加密。 然后，当没有由第二设备从外部存储器中检索数据，该数据被选择性地解密仅当所述第二设备被识别为安全的。

公开(公告)号：EP1507414B1

公开(公告)日：2008-04-30

申请号：EP03255093.1

申请日：2003-08-15

Applicant: STMicroelectronics Limited

Inventor： Dellow, Andrew ,  Bennett, Peter

IPC: H04N7/16 ,  G06F12/14

CPC classification number: G06F12/1483 ,  H04N21/443 ,  H04N21/4623

公开(公告)号：EP1748343A1

公开(公告)日：2007-01-31

申请号：EP05254795.7

申请日：2005-07-29

Applicant: STMicroelectronics Limited

Inventor： Dellow, Andrew

IPC: G06F1/00

CPC classification number: G06F21/70 ,  G06F21/73

Abstract: In a first aspect, the invention comprises a method for distributing personalised circuits (1) to one or more parties. First, a generic circuit (1) is distributed to each party. Then, a unique personalisation value is transmitted from each party to an authority (3). Next, each personalisation value received from each party is encrypted using a secret encryption key associated with the authority (3). Each encrypted personalisation value is then transmitted back to the corresponding party that sent each personalisation value. Each party then stores the encrypted personalisation value in their circuit (1). The stored encrypted personalisation value allows a piece of software to be properly executed by the circuit (1). In a second aspect, the invention comprises a semiconductor integrated circuit (1) arranged to execute a piece of software. The software requires a predetermined personalisation value as an input parameter to execute properly. The circuit comprises a personalisation memory (5) arranged to store an encrypted personalisation value; a key memory (7) for storing a decryption key; a personalisation control unit (11) comprising a cryptographic circuit (13) arranged to decrypt the encrypted personalisation value using the decryption key; and a processor (10) arranged to receive the decrypted personalisation value from the cryptographic circuit (13), to execute the software and to supply the software with the decrypted personalisation value.

Abstract translation: 在第一方面，本发明包括一种用于将个性化电路（1）分配给一个或多个方的方法。 首先，将通用电路（1）分配给各方。 然后，从每一方传送一个独特的个性化价值给一个权威机构（3）。 接下来，使用与权限（3）相关联的秘密加密密钥对从各方接收的每个个性化值进行加密。 然后将每个加密的个性化值发送回发送每个个性化值的相应方。 每一方然后将加密的个性化值存储在其电路（1）中。 存储的加密个性化值允许一个软件由电路（1）正确地执行。 在第二方面，本发明包括被配置为执行一段软件的半导体集成电路（1）。 该软件需要一个预定的个性化值作为输入参数来正确执行。 该电路包括个性化存储器（5），其被设置为存储加密的个性化值; 用于存储解密密钥的密钥存储器（7） 个性化控制单元（11），包括密码电路（13），其被配置为使用所述解密密钥来解密所述加密的个性化值; 以及处理器（10），被配置为从所述密码电路（13）接收所解密的个性化值，以执行所述软件并向所述软件提供所解密的个性化值。

公开(公告)号：EP1333350A1

公开(公告)日：2003-08-06

申请号：EP02250644.8

申请日：2002-01-30

Applicant: STMicroelectronics Limited

Inventor： Dellow, Andrew

IPC: G06F1/00

CPC classification number: G06F21/575 ,  G06F21/64

Abstract: A semiconductor integrated circuit includes a processor for executing application code from a memory and a verifier processor arranged to receive the application code via the same internal bus as the processor. The verifier processor performs a verification function to check that the application code is authentic. The verifier processor runs autonomously and cannot be spoofed as it receives the application code via the same internal bus as the main processor.

Abstract translation: 半导体集成电路包括用于从存储器执行应用代码的处理器和被布置为经由与处理器相同的内部总线接收应用代码的验证器处理器。 验证者处理器执行验证功能以检查应用代码是否可信。 验证器处理器自主运行，并且不会被欺骗，因为它通过与主处理器相同的内部总线接收应用程序代码。

公开(公告)号：EP1263139A2

公开(公告)日：2002-12-04

申请号：EP02253697.3

申请日：2002-05-27

Applicant: STMicroelectronics Limited

Inventor： Dellow, Andrew ,  Elliot, Paul

IPC: H03K17/00 ,  G06F1/08

CPC classification number: G06F1/08 ,  H03K5/1252 ,  H03K17/005

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed (20,22) relative to clock A to give a signal P, is then retimed (24,26) relative to clock B to give a signal Q, and finally is retimed (28,30) relative to clock A to give a signal R. Selector circuitry (34,40,42) operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate (34), are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract translation: 用于根据切换请求信号选择第一时钟信号A或第二时钟信号B的时钟源选择器包括三个重新定时电路，每个由两个时钟触发器组成。 首先，切换请求信号相对于时钟A被重新定时（20,22），以给出信号P，相对于时钟B被重新定时（24,26），给出一个信号Q，最后被重定时（28,30）相对 到时钟A给出信号R.选择器电路（34,40,42）的操作使得当信号Q被确定时，第二时钟信号B被输出，当信号P和信号R都不由NOR门（ 34）被断言，第一时钟信号A被输出，并且在其他时间输出零电平。 时钟源选择器可用于集成电路中以形成无毛刺多路复用器。