公开(公告)号：EP0957429A1

公开(公告)日：1999-11-17

申请号：EP98309735.3

申请日：1998-11-27

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G06F11/00

CPC classification number: G06F11/0763 ,  G01R31/31855

Abstract: An integrated circuit comprises a connection port having a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic, and a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins. The test access port controller is connectable to the test logic in a first mode of operation to effect communication of serial test data under control of an incoming clock signal and being operable in a second mode of operation to communication data as a sequence of serial bits according to a predetermined protocol between the connection port and the on-chip functional circuitry. The integrated circuit includes error detection means for detecting an error condition in the protocol and gating circuitry responsive to detection of the error condition to prevent communication of subsequent data until the error condition is detected as having been removed.

Abstract translation: 集成电路包括具有串行数据输入引脚和串行数据输出引脚，片上功能电路和测试逻辑的连接端口以及连接用于通过所述输入端通过芯片边界实现串行数据的通信的测试访问端口控制器，以及 输出引脚。 测试访问端口控制器可以在第一操作模式下连接到测试逻辑，以在输入时钟信号的控制下实现串行测试数据的通信，并且可以在第二操作模式中操作以通信数据作为串行位序列 到连接端口和片上功能电路之间的预定协议。 集成电路包括用于检测协议中的错误状况和门控电路的错误检测装置，其响应于错误状况的检测，以防止后续数据的通信，直到检测到错误状态已被去除。

公开(公告)号：EP0702241B1

公开(公告)日：2004-05-12

申请号：EP95305861.7

申请日：1995-08-22

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G01R31/3173 ,  G01R31/3185 ,  G06F11/24 ,  G06F11/267 ,  H03K3/037

CPC classification number: G06F11/2236 ,  G01R31/31858 ,  H03K3/0375

公开(公告)号：EP0957429B1

公开(公告)日：2003-01-22

申请号：EP98309735.3

申请日：1998-11-27

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G06F11/00

CPC classification number: G06F11/0763 ,  G01R31/31855

Abstract: An integrated circuit comprises a connection port having a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic, and a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins. The test access port controller is connectable to the test logic in a first mode of operation to effect communication of serial test data under control of an incoming clock signal and being operable in a second mode of operation to communication data as a sequence of serial bits according to a predetermined protocol between the connection port and the on-chip functional circuitry. The integrated circuit includes error detection means for detecting an error condition in the protocol and gating circuitry responsive to detection of the error condition to prevent communication of subsequent data until the error condition is detected as having been removed.

公开(公告)号：EP0849669B1

公开(公告)日：2001-11-14

申请号：EP97310066.2

申请日：1997-12-12

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G06F11/00

CPC classification number: G06F11/3648

公开(公告)号：EP0849668B1

公开(公告)日：2001-07-25

申请号：EP97310061.3

申请日：1997-12-12

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G06F11/00

CPC classification number: G06F11/3648

公开(公告)号：EP1832887A1

公开(公告)日：2007-09-12

申请号：EP07075256.3

申请日：1997-10-20

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G01R31/3185

CPC classification number: G01R31/318555 ,  G01R31/318572

Abstract: There is disclosed a test access port controller for effecting communications across a chip boundary having a test mode and a diagnostic mode of operation, wherein in the test mode of operation the test data is resultant data from a test operation having an expected and time delayed relationship, and in the diagnostic mode of operation diagnostic data is conveyed both on and off chip in the form of respective independent input and output serial bit streams simultaneously through the test access port controller.

Abstract translation: 公开了一种用于实现具有测试模式和诊断操作模式的芯片边界通信的测试访问端口控制器，其中在测试操作模式下，测试数据是具有预期和时间延迟关系的测试操作的结果数据 ，并且在诊断诊断模式下，诊断数据通过测试访问端口控制器同时以相应的独立输入和输出串行比特流的形式传送开和关芯片。

公开(公告)号：EP1615106A1

公开(公告)日：2006-01-11

申请号：EP04254030.2

申请日：2004-07-05

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert ,  Smith, David

IPC: G06F1/24

CPC classification number: G06F1/24

Abstract: An electronic device having first circuitry (2) operating in a first clock environment (clk1) and second circuitry (33) operating in a second clock environment (clk2) the first circuitry (2) being arranged to generate a soft reset signal for resetting the second circuitry (33) the integrated circuit (11) further comprising: a soft reset hold circuit (3) clocked in the first clock environment (clk1) connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchroniser (5) clocked in the second clock environment (clk2) connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.

Abstract translation: 一种具有在第一时钟环境（clk1）中操作的第一电路（2）和在第二时钟环境（clk2）中工作的第二电路（33））的电子设备，所述第一电路（2）被布置成产生软复位信号，以复位 第二电路（33）还包括：软复位保持电路（3），其在第一时钟环境（clk1）中被连接以接收软复位信号并产生处于断言状态的输出复位信号; 以及在第二时钟环境（clk2）中被时钟的同步器（5），其连接以接收输出复位信号，并且在预定时段之后产生处于断言状态的重新定时复位信号，其中重新定时复位信号被反馈到软复位保持 电路，用于使所述输出复位信号在所述预定周期结束时采用无效状态。

公开(公告)号：EP1584939A1

公开(公告)日：2005-10-12

申请号：EP04252078.3

申请日：2004-04-07

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert ,  Mills, Robert M.

IPC: G01R31/3185 ,  G01R31/319 ,  G06F1/04

CPC classification number: G01R31/318552

Abstract: An integrated circuit comprising test circuitry, the test circuitry comprising a counter for counting clock signals and having an output for providing a control signal. The counter being arranged to have an internal state, and the counter being arranged to change the control signal on the internal state of counter reaching a predetermined value.

Abstract translation: 一种包括测试电路的集成电路，所述测试电路包括用于对时钟信号进行计数并具有用于提供控制信号的输出的计数器。 计数器被布置成具有内部状态，并且该计数器被布置成在计数器的内部状态上改变控制信号达到预定值。

公开(公告)号：EP1584938A1

公开(公告)日：2005-10-12

申请号：EP04252076.7

申请日：2004-04-07

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert ,  Mills, Robert M.

IPC: G01R31/3185

CPC classification number: G01R31/318552

Abstract: An integrated circuit comprising: functional circuitry; test circuitry connected to the functional circuitry, wherein the test circuitry is arranged to control the testing of the functional circuitry; and clock signal generating circuitry connected to both the functional circuitry and the test circuitry. Wherein the test circuitry is arranged to use the clock signal for testing the functional circuitry.

Abstract translation: 一种集成电路，包括：功能电路; 连接到所述功能电路的测试电路，其中所述测试电路被布置成控制所述功能电路的测试; 以及连接到功能电路和测试电路两者的时钟信号发生电路。 其中测试电路被设置为使用时钟信号来测试功能电路。

公开(公告)号：EP0702239B1

公开(公告)日：2004-07-21

申请号：EP95305859.1

申请日：1995-08-22

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G01R31/3173 ,  G01R31/3185 ,  G06F11/24 ,  G06F11/267

CPC classification number: G01R31/318555 ,  G06F11/2273

Abstract: A test access port controller is provided for implementing scan testing with a chain of scan latches on an integrated circuit. The test access port controller can implement a structural test or a performance test. Selection between the two types of test is achieved through logic circuitry of the test access port controller. An integrated circuit and a test system are also provided.