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    Time interleaved digital signal processing in a read channel with reduced noise figure
    14.
    发明公开
    Time interleaved digital signal processing in a read channel with reduced noise figure 有权
    Zeitverschachteltes digitales Signalverarbeitungsverfahren在einem Lesekanal mit reduziertem Rauschmass

    公开(公告)号：EP1006525A1

    公开(公告)日：2000-06-07

    申请号：EP98830718.7

    申请日：1998-12-01

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bruccoleri, Melchiorre ,  Demicheli, Marco ,  Ottini, Daniele ,  Savo, Alessandro

    IPC: G11B20/00

    CPC classification number: G11B20/10277 ,  G11B20/10509

    Abstract: A read and analog-to-digital data conversion channel comprising preamplifying circuits (Pre-Amp), automatic gain control circuits (VGA), harmonics filters (MRA), equalizing low pass filters (LPF), a time interleaved analog-to-digital converter (INTERLEAVED ATOD) including a pair of identical analog/digital converters (ATOD_EVEN, ATOD_ODD) functioning in parallel and at a half clock frequency, subdividing the signal path into two parallel paths through said two identical converters, one for even bits and the other for odd bits, and a digital post-processing block (DIGITAL Post Processing) fed by two output streams of said time interleaved converter (INTERLEAVED ATOD) and outputting a reconstructed data stream (DATA) and controlling said circuits, through dedicated digital-to-analog converters (DAC_VGA, DAC_MRA, DAC_FC, DAC_BOOST), means for compensating the offset of the digital-to-analog converters contained in said pair of identical analog-to-digital converters (ATOD_EVEN, ATOD_ODD) of said time interleaved converter (INTERLEAVED ATOD), controlled by said post-processing block (DIGITAL Post Processing) through a digital-to-analog converter, further comprises two distinct offset compensating circuits, each composed of an offset compensating stage (OFFSET_EVEN_STAGE, OFFSET_ODD_STAGE) independently controlled by said digital post-processing block through a dedicated digital-to-analog converter (DAC_OFF_E, DAC_OFF_O), preventing appearance of spurious patterns in frequency domain.

    Abstract translation: 读和模数转换通道，包括前置放大电路（Pre-Amp），自动增益控制电路（VGA），谐波滤波器（MRA），均衡低通滤波器（LPF），时间交错模数转换 转换器（INTERLEAVED ATOD）包括一对并行和半个时钟频率工作的一对相同的模拟/数字转换器（ATOD_EVEN，ATOD_ODD），将信号路径细分为通过所述两个相同转换器的两个并行路径，一个用于偶数位，另一个用于偶数位 以及由所述时间交织转换器（INTERLEAVED ATOD）的两个输出流馈送的数字后处理块（DIGITAL Post Processing），并输出重构数据流（DATA）并通过专用数字 - 模拟转换器（DAC_VGA，DAC_MRA，DAC_FC，DAC_BOOST），用于补偿包含在所述相同模数转换器对（ATOD_EVEN，ATOD_ODD）中的数/模转换器的偏移量的装置 由所述后处理块（DIGITAL后处理）通过数模转换器控制的所述时间交织转换器（INTERLEAVED ATOD）还包括两个不同的偏移补偿电路，每个偏移补偿电路由偏移补偿级（OFFSET_EVEN_STAGE，OFFSET_ODD_STAGE ）通过专用数模转换器（DAC_OFF_E，DAC_OFF_O）独立地由所述数字后处理块控制，从而防止在频域中出现杂散模式。

    Method and device for delaying selected transitions in a digital data stream
    19.
    发明公开
    Method and device for delaying selected transitions in a digital data stream 有权
    Verfahren und Vorrichtung zumVerzögerndefinierterÜbergängein einem digitalen Datenstrom

    公开(公告)号：EP1014362A1

    公开(公告)日：2000-06-28

    申请号：EP98830756.7

    申请日：1998-12-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Demicheli, Marco ,  Bruccoleri, Melchiorre ,  Malfa, Maurizio ,  Bollati, Giacomino

    IPC: G11B20/10

    CPC classification number: G11B20/10009 ,  G11B5/012 ,  G11B5/09

    Abstract: A method of delaying by a certain time interval (Δwp) a transition in a digital data stream (O) fed to a write head of a mass storage device when said transition occurs at a clock phase following the one during which a preceding transition has occurred, for pre-compensating intersymbolic nonlinear interference effects suffered when reading the stored data, comprises feeding to a first circuit (CC1) a digital data stream (I) to be stored and a clock signal (Ck) and outputting from said first circuit (CC1) a pair of digital streams (N, R), a first stream (N) assuming a first logic value every time a transition of said input stream occurs during a clock phase not successive to a clock phase during which a transition of said input stream (I) has occurred, the second stream (R) assuming said first logic value every time a transition of said input stream (I) occurs during a clock phase following a clock phase during which a transition has taken place in said input stream (I); feeding said two digital stream (N, R) and said clock signal (Ck) to as many inputs of a second circuit (DC1) and outputting from said second circuit said digital data stream (O) directed to the write head, in which the transitions immediately following a preceding transition are delayed by said pre-established time interval (Δwp), by sampling the two digital streams (N, R) with a pair of flip-flops (FN2, FR2), each of which is respectively timed by clock signals respectively delayed by a certain different time interval (Δn, Δr) and such that the difference between said different delay intervals is equal to said pre-established time interval ( Δn-Δr=Δwp ) and recombining the signals output from said pair of flip-flops (FN2, FR2) through an logic XOR gate (X1) into said digital data stream (O).

    Abstract translation: 一种在一个时间间隔（DELTA wp）下延迟当馈送到大容量存储设备的写入头的数字数据流（O）中的转变时的方法，当所述转换发生在与之前的转换有关的时钟阶段 发生在用于在读取存储的数据时遭受的预补偿后的并非非线性干扰效应的情况下，包括馈送到要存储的数字数据流（I）的第一电路（CC1）和时钟信号（Ck），并从所述第一电路 CC1）一对数字流（N，R），每当在不连续到所述输入的转换的时钟相位的时钟相位期间发生所述输入流的转变时，假设第一逻辑值的第一流（N） 流（I）发生时，每当在所述输入流中发生转换的时钟相位之后的时钟相位期间发生所述输入流（I）的转变时，假定所述第一逻辑值的第二流（R） 一世）; 将所述两个数字流（N，R）和所述时钟信号（Ck）馈送到第二电路（DC1）的多个输入，并从所述第二电路输出指向写入头的所述数字数据流（O），其中 通过用一对触发器（FN2，FR2）对两个数字流（N，R）进行采样来分别定时，将在先前转换之后立即进行的转换延迟所述预先设定的时间间隔（DELTA wp） 通过分别延迟了一定的不同时间间隔（DELTA n，DELTA r）的时钟信号，并且使得所述不同延迟间隔之间的差值等于所述预先建立的时间间隔（DELTA n-DELTA r = DELTA wp），并将 从所述一对触发器（FN2，FR2）通过逻辑异或门（X1）输出到所述数字数据流（O）中的信号。

    Flash analog-to-digital converter
    20.
    发明公开
    Flash analog-to-digital converter 有权
    闪光模拟数字电视

    公开(公告)号：EP1005170A1

    公开(公告)日：2000-05-31

    申请号：EP98830712.0

    申请日：1998-11-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ottini, Daniele ,  Bruccoleri, Melchiorre ,  Bollati, Giacomino ,  Demicheli, Marco

    IPC: H03M1/36 ,  H03M7/16

    CPC classification number: H03M1/0809 ,  H03M1/365

    Abstract: A flash analog-to-digital converter comprising a bank of comparators (COMPi) with a differential output, generating a thermometric code and a bank of three-input (A,B,C) logic NOR gates (NORj) for correcting errors in said thermometric code, has enhanced immunity to noise and reduced imprecisions, especially at high conversion rates upon occurence of metastability within the comparators, by providing for a passive interface constituted by a plurality of voltage dividers (Ra-Rb), each connected between the noninverted output (out_p) of a respective comparator (COMPi) and the inverted output (out_n) of the comparator of higher order (COMPi+1) of said bank; a corresponding logic NOR gate (NORj) of said bank having a first input (A) coupled to the inverted output (out_n) of said respective comparator (COMPi-1), a second input (B) coupled to the noninverted output (out_p) of said comparator (COMPi) of higher order and a third input (C) coupled to an intermediate tap of said voltage divider (Ra-Rb).

    Abstract translation: 一种闪存模数转换器，包括具有差分输出的一组比较器（COMPi），产生一个温度测量代码和一组三输入（A，B，C）逻辑或非门（NORj），用于校正所述 通过提供由多个分压器（Ra-Rb）构成的无源接口，每个连接在非反相输出端（Ra-Rb）之间，具有增强的抗噪声能力和减小的不精确性，特别是在比较器内发生亚稳态时的高转换速率 （COMPi）和所述存储体的高阶比较器（COMPi + 1）的反相输出（out_n）的输出（out_p） 所述存储体的对应逻辑或非门（NORj）具有耦合到所述各个比较器（COMPi-1）的反相输出（out_n）的第一输入（A），耦合到非反相输出（out_p）的第二输入（B） 的比较器（COMPi）和耦合到所述分压器（Ra-Rb）的中间抽头的第三输入端（C）。

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