公开(公告)号：EP1020990A2

公开(公告)日：2000-07-19

申请号：EP99830379.6

申请日：1999-07-17

Applicant: STMicroelectronics S.r.l.

Inventor： Marchese, Stefano ,  Bollati, Giacomino ,  Malfa, Maurizio ,  Savo, Pierandrea

IPC: H03F3/45

CPC classification number: H03F3/45632 ,  H03F3/45197 ,  H03F2203/45466

Abstract: A transconductor comprising a differential stage composed of a pair of input transistors, a resistive line of degeneration convecting the sources of the input transistors of said differential stage, a pair of bias current generators, each coupled between the source of a respective input transistor and a common ground node, has said resistive line of degeneration composed of one or more transistors in series, the gate of which is coupled to a voltage at least equal to the common mode voltage of the differential stage, and which are sized to operate in the triode region.

Abstract translation: 一种跨导体，包括由一对输入晶体管组成的差分级，与所述差分级的输入晶体管的源极对流的电阻线，一对偏置电流发生器，每个偏置电流发生器耦合在相应的输入晶体管的源极和 公共接地节点具有由串联的一个或多个晶体管组成的退化电阻线，其栅极耦合到至少等于差分级的共模电压的电压，并且其尺寸被设计成在三极管中工作 地区。

公开(公告)号：EP1014362A1

公开(公告)日：2000-06-28

申请号：EP98830756.7

申请日：1998-12-15

Applicant: STMicroelectronics S.r.l.

Inventor： Demicheli, Marco ,  Bruccoleri, Melchiorre ,  Malfa, Maurizio ,  Bollati, Giacomino

IPC: G11B20/10

CPC classification number: G11B20/10009 ,  G11B5/012 ,  G11B5/09

Abstract: A method of delaying by a certain time interval (Δwp) a transition in a digital data stream (O) fed to a write head of a mass storage device when said transition occurs at a clock phase following the one during which a preceding transition has occurred, for pre-compensating intersymbolic nonlinear interference effects suffered when reading the stored data, comprises feeding to a first circuit (CC1) a digital data stream (I) to be stored and a clock signal (Ck) and outputting from said first circuit (CC1) a pair of digital streams (N, R), a first stream (N) assuming a first logic value every time a transition of said input stream occurs during a clock phase not successive to a clock phase during which a transition of said input stream (I) has occurred, the second stream (R) assuming said first logic value every time a transition of said input stream (I) occurs during a clock phase following a clock phase during which a transition has taken place in said input stream (I); feeding said two digital stream (N, R) and said clock signal (Ck) to as many inputs of a second circuit (DC1) and outputting from said second circuit said digital data stream (O) directed to the write head, in which the transitions immediately following a preceding transition are delayed by said pre-established time interval (Δwp), by sampling the two digital streams (N, R) with a pair of flip-flops (FN2, FR2), each of which is respectively timed by clock signals respectively delayed by a certain different time interval (Δn, Δr) and such that the difference between said different delay intervals is equal to said pre-established time interval ( Δn-Δr=Δwp ) and recombining the signals output from said pair of flip-flops (FN2, FR2) through an logic XOR gate (X1) into said digital data stream (O).

Abstract translation: 一种在一个时间间隔（DELTA wp）下延迟当馈送到大容量存储设备的写入头的数字数据流（O）中的转变时的方法，当所述转换发生在与之前的转换有关的时钟阶段 发生在用于在读取存储的数据时遭受的预补偿后的并非非线性干扰效应的情况下，包括馈送到要存储的数字数据流（I）的第一电路（CC1）和时钟信号（Ck），并从所述第一电路 CC1）一对数字流（N，R），每当在不连续到所述输入的转换的时钟相位的时钟相位期间发生所述输入流的转变时，假设第一逻辑值的第一流（N） 流（I）发生时，每当在所述输入流中发生转换的时钟相位之后的时钟相位期间发生所述输入流（I）的转变时，假定所述第一逻辑值的第二流（R） 一世）; 将所述两个数字流（N，R）和所述时钟信号（Ck）馈送到第二电路（DC1）的多个输入，并从所述第二电路输出指向写入头的所述数字数据流（O），其中 通过用一对触发器（FN2，FR2）对两个数字流（N，R）进行采样来分别定时，将在先前转换之后立即进行的转换延迟所述预先设定的时间间隔（DELTA wp） 通过分别延迟了一定的不同时间间隔（DELTA n，DELTA r）的时钟信号，并且使得所述不同延迟间隔之间的差值等于所述预先建立的时间间隔（DELTA n-DELTA r = DELTA wp），并将 从所述一对触发器（FN2，FR2）通过逻辑异或门（X1）输出到所述数字数据流（O）中的信号。

公开(公告)号：EP1014362B1

公开(公告)日：2003-11-19

申请号：EP98830756.7

申请日：1998-12-15

Applicant: STMicroelectronics S.r.l.

Inventor： Demicheli, Marco ,  Bruccoleri, Melchiorre ,  Malfa, Maurizio ,  Bollati, Giacomino

IPC: G11B20/10

CPC classification number: G11B20/10009 ,  G11B5/012 ,  G11B5/09

公开(公告)号：EP1020990A3

公开(公告)日：2000-08-02

申请号：EP99830379.6

申请日：1999-07-17

Applicant: STMicroelectronics S.r.l.

Inventor： Marchese, Stefano ,  Bollati, Giacomino ,  Malfa, Maurizio ,  Savo, Pierandrea

IPC: H03F3/45

CPC classification number: H03F3/45632 ,  H03F3/45197 ,  H03F2203/45466

Abstract: A transconductor comprising a differential stage composed of a pair of input transistors, a resistive line of degeneration convecting the sources of the input transistors of said differential stage, a pair of bias current generators, each coupled between the source of a respective input transistor and a common ground node, has said resistive line of degeneration composed of one or more transistors in series, the gate of which is coupled to a voltage at least equal to the common mode voltage of the differential stage, and which are sized to operate in the triode region.

Abstract translation: 一种跨导器，包括由一对输入晶体管构成的差分级，一个对所述差分级的输入晶体管的源极进行对流的负反馈电阻线，一对偏置电流发生器，每个偏置电流发生器耦合在相应输入晶体管的源极和 共同的接地节点具有由串联的一个或多个晶体管构成的电阻性退化线，其栅极耦合到至少等于差分级的共模电压的电压，并且其尺寸被设定为在三极管 地区。