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    Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors, with salicided junctions
    12.
    发明公开
    Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors, with salicided junctions 有权
    具有EEPROM存储器单元，高压晶体管并与Silizidanschlüssen低压晶体管，以及制造方法中的相同的电子设备

    公开(公告)号：EP0986100A1

    公开(公告)日：2000-03-15

    申请号：EP98830645.2

    申请日：1998-10-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

    IPC: H01L21/8239 ,  H01L27/105

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11529

    Abstract: A method for manufacturing electronic devices, comprising memory cells (72) and LV transistors (70) with salicided junctions, comprising, in sequence, the steps of: depositing an upper layer (43) of polycrystalline silicon; defining the upper layer, obtaining floating gate regions (43b) on first areas, LV gate regions (43a) on second areas (13) of a substrate (2), and undefined regions (43) on the first and third areas of the substrate; forming first cell source regions (49 and 50) laterally to the floating gate regions (43b); forming LV source and drain regions (55) laterally to the LV gate regions; forming a silicide layer (57a1, 57a2, 57) on the LV source and drain regions (55), on the LV gate regions (43a), and on the undefined portions (43); defining HV gate regions (43d) on the third areas, and selection gate regions (43c) on the first areas (14); forming source regions (65a) laterally to the selection gate regions (43c), and source and drain regions (64) laterally to the HV gate regions.

    Abstract translation: 一种用于制造电子器件，其包括存储单元（72）和LV晶体管（70）与金属硅化结，其包括，在序列的方法，下列步骤：多晶硅的上层（43）的存入; ，定义上层，获得浮置栅极上的第一种区域的区域（43B），对在基片上的第一和第三区域一个基板（2）的第二区域（13），以及未定义区（43）LV栅极区域（43A） ; 形成第一单元的源极区（49和50）尾盘反弹到浮栅区域（43B）; 形成LV源和漏区（55）尾盘反弹到LV栅极区; 形成上的LV栅极区域（43A）的LV源和漏区（55）的硅化物层（57a1，57a2，57），并在未定义部分（43）; 在第三区域HV-限定栅区（43D），并在所述第一区域的选择栅极区域（43C）（14）; 形成源极区（65A）尾盘反弹到选择栅极区域（43C），以及源极和漏极区（64）尾盘反弹到HV栅极区域。

    Method of fabrication a non-volatile semiconductor memory device with shielded single polysilicon gate memory part
    14.
    发明公开
    Method of fabrication a non-volatile semiconductor memory device with shielded single polysilicon gate memory part 失效
    制造非易失性半导体存储装置的方法与屏蔽Einpolysiliziumgate存储部

    公开(公告)号：EP0889520A1

    公开(公告)日：1999-01-07

    申请号：EP97830334.5

    申请日：1997-07-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bottini, Roberta ,  Dalla Libera, Giovanna ,  Vajana, Bruno ,  Pio, Federico

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558

    Abstract: Process for manufacturing a semiconductor memory device comprising the formation, in a same semiconductor material chip, of at least a first memory cell (18) comprising a MOS transistor (19) with a first gate electrode (21) and a second gate electrode (23) superimposed and respectively formed by definition in a first (12) and a second layer (17) of conductive material, and of at least a second memory cell (1) shielded by a layer (32) of shielding material for preventing the information stored in the second memory cell (1) from being accessible from the outside, said second memory cell (1) comprising a MOS transistor (2) with a floating gate electrode (4) formed simultaneously with the first gate electrode (21) of the first cell (18) by definition of said first layer of conductive material (12). Said layer of shielding material (32) is formed by definition of said second layer of conductive material (17).

    Abstract translation: 处理用于制造半导体存储器件，包括形成，在相同的半导体材料芯片，至少一个第一存储单元（18）包括具有第一栅电极（21）和第二栅电极的MOS晶体管（19）（23 ）屏蔽材料用于防止存储的信息的叠加并分别在第一（12根据定义形成的）和导电材料的第二层（17），以及至少一个第二存储单元的（1由一个层（32屏蔽）） 在从外部被访问的第二存储单元（1），所述第二存储器单元（1），其包含（2）与浮置栅电极（4）与所述第一的第一栅电极（21）同时形成的MOS晶体管 细胞（18）通过所述第一导电材料（12）的层的定义。 屏蔽材料（32）的所述层是通过导电材料（17）的所述第二层的定义形成。

    Method for obtaining a multi-value ROM in an EEPROM process flow
    17.
    发明公开
    Method for obtaining a multi-value ROM in an EEPROM process flow 审中-公开
    一种用于通过一种制备一个EEPROM存储器制备仅多元存储器（ROM）工艺

    公开(公告)号：EP1024527A3

    公开(公告)日：2001-05-23

    申请号：EP99126235.3

    申请日：1999-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

    IPC: H01L21/8246 ,  H01L21/8247

    CPC classification number: H01L27/112 ,  G11C11/56 ,  G11C11/5692 ,  H01L27/11293

    Abstract: Presented is a method for obtaining a multi-level ROM in a dual gate EEPROM process flow. The method begins with, on a semiconductor substrate, defining active areas respectively for transistors of ROM cells, transistors of electrically erasable non-volatile memory cells, and additional transistors of the storage circuitry. Then, integrated capacitors are integrated in the storage circuit. According to this method, during the implanting step for forming integrated capacitors, at least an active area of the ROM cell is similarly implanted.

    Abstract translation: 提出了一种在双栅极EEPROM处理流程获取多级ROM的方法。 该方法开始于，在一个半导体衬底，活性定义分别领域ROM单元，电可擦除非易失性存储器单元的晶体管，以及所述存储电路的附加晶体管的晶体管。 然后，整合电容器被集成在存储电路。 。根据该方法，在用于形成集成电容器的注入步骤，至少在所述RO​​M单元的有源区被类似地植入。

    Process for manufacturing an electronic device comprising EEPROM memory cells with dimensional control of the floating gate regions
    18.
    发明公开
    Process for manufacturing an electronic device comprising EEPROM memory cells with dimensional control of the floating gate regions 审中-公开
    一种用于根据在浮置栅极区域的尺寸的控制产生具有EEPROM存储单元的半导体器件的工艺

    公开(公告)号：EP1071134A1

    公开(公告)日：2001-01-24

    申请号：EP99830470.3

    申请日：1999-07-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Vajana, Bruno ,  Dalla Libera, Giovanna

    IPC: H01L27/115 ,  H01L29/788 ,  H01L21/8247 ,  H01L21/28

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324

    Abstract: The manufacturing process comprises the steps of: forming a substrate (2), an insulating layer (24, 26) including a tunnel area (26); simultaneously forming a floating gate region (35") of a memory transistor and a lower gate portion (35') of a selection transistor. The floating gate region (35") internally forms a hole (37), one side of which (35b) delimits, together with an external side (35a) of the floating gate region, a portion of tunnel arranged above the tunnel area (26). A dielectric material layer (40) is then deposited, and fills the hole (37) of the floating gate region (35"). Next, the structure is plagiarized by CMP, and an insulating region (41) of dielectric material is formed. Then, a control gate region (50a) is formed above the floating gate region (35") and simultaneously an upper gate portion is formed above the lower gate portion (35'). The upper and lower gate portions (50b) form a control gate region of the selection transistor (81). In this way, the upper gate portion (50b) and the control gate region (50a) are substantially on a same level.

    Abstract translation: 制造过程包括以下步骤：形成（2），在绝缘包括隧道区域（26）层（24，26）一衬底; 同时形成的浮置栅极区域（35“）的选择晶体管的存储晶体管和下门部分（35“），该浮置栅极区域（35" ）在内部形成一个孔（37），其一侧（35B ）界定，连同（在外部侧（35A）的浮栅区的，设置在隧道区域26）上述隧道的一部分。 然后，将介电材料层（40）沉积，并填充浮置栅极区域（35“）。接下来的孔（37），该结构通过CMP剽窃，以及绝缘介电材料的区域（41）形成。 然后，控制栅极区域（50A）的浮置栅极区域（35“）的上方形成，并同时上栅极部分的下部栅极部分（35“）的上方形成。 上部和下部栅极部分（50B）形成的选择晶体管（81）的控制栅极区域。 以这种方式，上栅极部分（50B）和所述控制栅极区域（50A）基本在同一水平上。

    Process for manufacturing electronic devices comprising nonvolatile memory cells with dimensional control of the floating gate regions
    19.
    发明公开
    Process for manufacturing electronic devices comprising nonvolatile memory cells with dimensional control of the floating gate regions 审中-公开
    一种用于通过在浮置栅极区域的尺寸控制的制造非易失性存储器单元的方法

    公开(公告)号：EP1058309A1

    公开(公告)日：2000-12-06

    申请号：EP99830346.5

    申请日：1999-06-04

    Applicant: STMicroelectronics S.r.l.

    Inventor： Dalla Libera, Giovanna ,  Vajana, Bruno ,  Patelmo, Matteo

    IPC: H01L27/115 ,  H01L29/788 ,  H01L21/8247

    CPC classification number: H01L27/11526 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/42324

    Abstract: The manufacturing process comprises the steps of: forming a first insulating region (25b) on top of an active area; forming a tunnel region (98) laterally to the first insulating region; forming a floating gate region (95); sealing the floating gate region with an insulating region (96; 34); forming a control gate region (43b) on top of the floating gate region; and forming conductive regions (65a, 65b) in the active area (14). The floating gate region (95) is obtained by depositing and defining a semiconductor material layer (27) through a floating gate mask (90). The floating gate mask (90) has an opening (92) with an internally delimiting side (90b) extending at a preset distance from a corresponding externally delimiting side (90a) of the mask, and the semiconductor material layer (27) is removed laterally at the external and internal delimiting sides so that the tunnel area (98) is defined, as regards its length, by the floating gate mask alone.

    Abstract translation: 制造过程包括以下步骤：形成在有源区之上的第一绝缘区域（25B）; 形成隧道区域（98）晚反弹至第一绝缘区域; 形成浮置栅极区域（95）; 密封与所述浮置栅极区域在绝缘区（96; 34）; 形成在浮置栅极区域的顶部上的控制栅极区域（43B）; 以及形成导电区域（65A，65B）在有源区（14）。 浮置栅极区域（95）是通过沉积和限定通过浮置栅极掩模（90）的半导体材料层（27）中获得。 浮栅掩模（90）具有在开口（92），在内部限定侧（90b）的在预先设定的距离从相应的外部界定掩模侧（90A），和半导体材料层（27）被去除尾盘反弹扩展 在外部和内部侧面界定所以做了隧道区域（98）被定义，作为单独关于其长度，由浮动栅极掩模。

    Process for manufacturing electronic devices comprising non-salicidated nonvolatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors
    20.
    发明公开
    Process for manufacturing electronic devices comprising non-salicidated nonvolatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors 审中-公开
    对于仅具有存储单元和这些都是未硅化高压晶体管，以及低电压晶体管具有以自对准Silizidübergang电子元件的制造方法

    公开(公告)号：EP0996152A1

    公开(公告)日：2000-04-26

    申请号：EP98830644.5

    申请日：1998-10-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

    IPC: H01L21/8239 ,  H01L27/105

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11546

    Abstract: The process permits the manufacture of LV transistors (80) with salicidated junctions on first areas (19) of a substrate (2), HV transistors (81) on second areas (14) and memory cells (82) on third areas (13). The process comprises the steps of: forming LV oxide regions (36) and LV gate regions (43a) on the first areas (19), HV oxide regions (34) on the second areas (14), selection oxide regions (34), tunnel oxide regions (26b) and matrix oxide regions (25b) on the third areas (13); forming floating gate regions (27b) and insulating regions (31b) on the tunnel oxide regions and the matrix oxide regions; forming first LV source and drain regions (55) laterally to the LV gate regions (43a); forming suicide regions (75a1, 75a2) on the first source and drain regions (55) and on the LV gate regions (43a); forming semiconductor material regions (43) completely covering the second and third areas (13, 14); and at the same time forming HV gate regions (43d) on the HV oxide regions, selection gate regions (43c) on the selection oxide regions and control gate regions (43b) on the insulating regions through a step of shaping the semiconductor material regions.

    Abstract translation: 方法允许LV晶体管（80）与基板（2）的上第一区域salicidated结（19）的制造中，HV晶体管（81）上的第二区域（14）和存储单元上的第三区域（82）（13） ， 该方法包括以下步骤：形成LV氧化区（36）和LV栅极区域（43A）上的第一区域（19），在所述第二区域（14），选择氧化物区域HV氧化区（34）（34） 隧道氧化物区域（26B）和基质氧化物的区域（25B）在所述第三区域（13）; 形成浮栅区（27b）的与绝缘区域（31B）上的隧道氧化物区域和基体氧化物区; 形成第一LV源和漏区（55）尾盘反弹到LV栅极区域（43A）; 形成硅化物区（75A1，75A2）在所述第一源极和漏极区（55）和在LV栅极区域（43A）; 形成半导体材料区（43）完全覆盖所述第二和第三区域（13，14）; 和在在HV氧化物区域，选择栅区（43C）上的绝缘区域的选择氧化区和控制栅极区域（43B）通过成形半导体材料区域的步骤中同时形成HV栅极区（43D）。

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