公开(公告)号：EP0994513B1

公开(公告)日：2004-02-25

申请号：EP98830614.8

申请日：1998-10-15

Applicant: STMicroelectronics S.r.l.

Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia, c/o STMicroelectronics S.r.l. ,  Vajana, Bruno

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

公开(公告)号：EP0994513A1

公开(公告)日：2000-04-19

申请号：EP98830614.8

申请日：1998-10-15

Applicant: STMicroelectronics S.r.l.

Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia, c/o STMicroelectronics S.r.l. ,  Vajana, Bruno

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

Abstract: The invention relates to a simplified non-DPCC process for the definition of the tunnel area in non-volatile memory cells with semi-conductor floating gate, which are non-aligned and incorporated in a matrix of cells with associated control circuitry, to each cell a selection transistor being associated, the process comprising at least the following phases:

growth or deposition of a dielectric layer of gate of the sensing transistor and of the cells;
tunnel mask for defining the area of tunnel;
cleaning etching of the dielectric layer of gate in the area of tunnel up to the surface of the semi-conductor;
growth of tunnel oxide;

Advantageously, the tunnel mask is extended above the region occupied by the selection transistor.

Abstract translation: 本发明涉及一种用于在非易失性存储器单元具有半导体浮动栅极，其是未对齐，并与相关的控制电路单元的矩阵掺入的隧道区域的定义简化的非DPCC过程中，给每个小区 一选择晶体管被关联，所述方法包括至少以下阶段：所述感测晶体管和所述单元的栅极的电介质层的生长或沉积; 隧道限定用于隧道的区域掩模; 清洁栅极介电层的蚀刻在隧道到半导体的表面的面积; 隧道氧化物的生长; 有利地，隧道掩模通过选择晶体管所占据的区域上方延伸。