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    Phase locked loop circuit and control method thereof
    11.
    发明公开
    Phase locked loop circuit and control method thereof 失效
    Phasenregelschleife und Verfahren zu deren Steuerung

    公开(公告)号：EP0957584A1

    公开(公告)日：1999-11-17

    申请号：EP98830300.4

    申请日：1998-05-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Celant, Luca ,  Demicheli, Marco ,  Bruccoleri, Melchiorre ,  Ottini, Daniele

    IPC: H03L7/089

    CPC classification number: H03L7/0893 ,  H03L7/0896

    Abstract: A phase locked ring comprising a phase comparator, a charge pumping circuit, a loop filter and a voltage controlled oscillator, where the loop filter comprises two input terminals connected with two symmetric branches of the charge pumping circuit, each symmetric branch comprising a constant current generator and a pulsed current generator. Feedback paths are provided to control constant current generators through the voltage available on both loop filter terminals. According to the present invention, pulsed current generators (I7, I8) are separated from the respective loop filter terminals (N1 , N2) by circuit breaking switching means (S1, S2), said circuit breaking switching means (S1, S2) being controlled by phase signals (UP, DOWN) outputted from the phase comparator (2).

    Abstract translation: 一种锁相环，包括相位比较器，电荷泵浦电路，环路滤波器和压控振荡器，其中环路滤波器包括与电荷泵浦电路的两个对称分支连接的两个输入端子，每个对称支路包括恒定电流发生器 和脉冲电流发生器。 提供反馈路径，通过两个环路滤波器端子上可用的电压来控制恒流发电机。 根据本发明，脉冲电流发生器（I7，I8）通过断路切换装置（S1，S2）与各个环路滤波器端子（N1，N2）分离，所述断路切换装置（S1，S2）被控制 通过从相位比较器（2）输出的相位信号（UP，DOWN）。

    High frequency track&hold full wave rectifier
    12.
    发明公开
    High frequency track&hold full wave rectifier 失效
    Verfolge- und Halte-Vollwellengleichrichterfürhochfrequente Signale

    公开(公告)号：EP0952455A1

    公开(公告)日：1999-10-27

    申请号：EP98830246.9

    申请日：1998-04-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bruccoleri, Melchiorre ,  Ottini, Daniele ,  Demicheli, Marco ,  Bollati, Giacomino

    IPC: G01R19/04

    CPC classification number: G01R19/22

    Abstract: A full-wave rectifier for monitoring the amplitude of a differential analog signal (IN+, IN-) is composed of a differential Track&Hold stage (T&H) controlled by a first differential logic timing signal (TClk+, TClk-), tracking the differential analog input signal (IN+, IN-) during a tracking phase that corresponds to a high logic stage of the first differential timing signal (TClk+, TClk-), producing a differential output signal that is a replica of the input signal and storing it during a successive storing phase that corresponds to a low logic state of the first differential timing signal (TClk+, TClk-); a first differential output amplifier ( ) having inputs coupled to the output of the Track&Hold stage (T&H); a differential bistable circuit (LATCH-ECL), controlled by a second differential logic timing signal (DClk+, DClk-), having inputs coupled to the differential outputs of the first amplifier ( ) and producing a third differential logic control signal (S+, S-); a second multiplexed amplifier (Analog-Amp ), controlled by the third differential control signal (S+, S-), having inputs coupled to the output of the Track&Hold stage (T&H) and outputting a differential analog signal (OUT+, OUT-) of amplitude function of the amplitude of the differential input signal (IN+, IN-); a timing circuit (T C ) receiving at an input a differential logic synchronism signal (Clk+, Clk-) and generating the first differential timing signal (TClk+, TClk-) of said Track&Hold stage (T&H) and the second differential timing signal (DClk+, DClk-) of said bistable circuit (LATCH-ECL).

    Abstract translation: 用于监视差分模拟信号（IN +，IN-）的幅度的全波整流器由由第一差分逻辑定时信号（TClk +，TClk-）控制的差分跟踪保持级（T＆H）组成，跟踪差分模拟输入 在对应于第一差分定时信号（TClk +，TClk-）的高逻辑级的跟踪阶段的信号（IN +，IN-）），产生作为输入信号的复制品的差分输出信号并在连续的期间存储 存储相位对应于第一差分定时信号（TClk +，TClk-）的低逻辑状态; 具有耦合到轨道和保持级（T＆amp; H）的输出的输入的第一差分输出放大器（@）; 由第二差分逻辑定时信号（DClk +，DClk-）控制的差分双稳态电路（LATCH-ECL）具有耦合到第一放大器（@）的差分输出的输入，并产生第三差分逻辑控制信号（S + S-）; 由第三差分控制信号（S +，S-）控制的第二多路复用放大器（Analog-Amp @），具有耦合到跟踪和保持级（T＆amp; H）的输出并输出差分模拟信号（OUT +，OUT-） 幅度函数的差分输入信号（IN +，IN-）的幅度; 定时电路（T @ C @）在输入端接收差分逻辑同步信号（Clk +，Clk-）并产生所述跟踪和保持级（T＆amp; H）的第一差分定时信号（TClk +，Tclk-）和第二差分定时信号 （LATCH-ECL）的（DClk +，DClk-）。

    Method and device for delaying selected transitions in a digital data stream
    16.
    发明公开
    Method and device for delaying selected transitions in a digital data stream 有权
    Verfahren und Vorrichtung zumVerzögerndefinierterÜbergängein einem digitalen Datenstrom

    公开(公告)号：EP1014362A1

    公开(公告)日：2000-06-28

    申请号：EP98830756.7

    申请日：1998-12-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Demicheli, Marco ,  Bruccoleri, Melchiorre ,  Malfa, Maurizio ,  Bollati, Giacomino

    IPC: G11B20/10

    CPC classification number: G11B20/10009 ,  G11B5/012 ,  G11B5/09

    Abstract: A method of delaying by a certain time interval (Δwp) a transition in a digital data stream (O) fed to a write head of a mass storage device when said transition occurs at a clock phase following the one during which a preceding transition has occurred, for pre-compensating intersymbolic nonlinear interference effects suffered when reading the stored data, comprises feeding to a first circuit (CC1) a digital data stream (I) to be stored and a clock signal (Ck) and outputting from said first circuit (CC1) a pair of digital streams (N, R), a first stream (N) assuming a first logic value every time a transition of said input stream occurs during a clock phase not successive to a clock phase during which a transition of said input stream (I) has occurred, the second stream (R) assuming said first logic value every time a transition of said input stream (I) occurs during a clock phase following a clock phase during which a transition has taken place in said input stream (I); feeding said two digital stream (N, R) and said clock signal (Ck) to as many inputs of a second circuit (DC1) and outputting from said second circuit said digital data stream (O) directed to the write head, in which the transitions immediately following a preceding transition are delayed by said pre-established time interval (Δwp), by sampling the two digital streams (N, R) with a pair of flip-flops (FN2, FR2), each of which is respectively timed by clock signals respectively delayed by a certain different time interval (Δn, Δr) and such that the difference between said different delay intervals is equal to said pre-established time interval ( Δn-Δr=Δwp ) and recombining the signals output from said pair of flip-flops (FN2, FR2) through an logic XOR gate (X1) into said digital data stream (O).

    Abstract translation: 一种在一个时间间隔（DELTA wp）下延迟当馈送到大容量存储设备的写入头的数字数据流（O）中的转变时的方法，当所述转换发生在与之前的转换有关的时钟阶段 发生在用于在读取存储的数据时遭受的预补偿后的并非非线性干扰效应的情况下，包括馈送到要存储的数字数据流（I）的第一电路（CC1）和时钟信号（Ck），并从所述第一电路 CC1）一对数字流（N，R），每当在不连续到所述输入的转换的时钟相位的时钟相位期间发生所述输入流的转变时，假设第一逻辑值的第一流（N） 流（I）发生时，每当在所述输入流中发生转换的时钟相位之后的时钟相位期间发生所述输入流（I）的转变时，假定所述第一逻辑值的第二流（R） 一世）; 将所述两个数字流（N，R）和所述时钟信号（Ck）馈送到第二电路（DC1）的多个输入，并从所述第二电路输出指向写入头的所述数字数据流（O），其中 通过用一对触发器（FN2，FR2）对两个数字流（N，R）进行采样来分别定时，将在先前转换之后立即进行的转换延迟所述预先设定的时间间隔（DELTA wp） 通过分别延迟了一定的不同时间间隔（DELTA n，DELTA r）的时钟信号，并且使得所述不同延迟间隔之间的差值等于所述预先建立的时间间隔（DELTA n-DELTA r = DELTA wp），并将 从所述一对触发器（FN2，FR2）通过逻辑异或门（X1）输出到所述数字数据流（O）中的信号。

    Flash analog-to-digital converter
    17.
    发明公开
    Flash analog-to-digital converter 有权
    闪光模拟数字电视

    公开(公告)号：EP1005170A1

    公开(公告)日：2000-05-31

    申请号：EP98830712.0

    申请日：1998-11-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ottini, Daniele ,  Bruccoleri, Melchiorre ,  Bollati, Giacomino ,  Demicheli, Marco

    IPC: H03M1/36 ,  H03M7/16

    CPC classification number: H03M1/0809 ,  H03M1/365

    Abstract: A flash analog-to-digital converter comprising a bank of comparators (COMPi) with a differential output, generating a thermometric code and a bank of three-input (A,B,C) logic NOR gates (NORj) for correcting errors in said thermometric code, has enhanced immunity to noise and reduced imprecisions, especially at high conversion rates upon occurence of metastability within the comparators, by providing for a passive interface constituted by a plurality of voltage dividers (Ra-Rb), each connected between the noninverted output (out_p) of a respective comparator (COMPi) and the inverted output (out_n) of the comparator of higher order (COMPi+1) of said bank; a corresponding logic NOR gate (NORj) of said bank having a first input (A) coupled to the inverted output (out_n) of said respective comparator (COMPi-1), a second input (B) coupled to the noninverted output (out_p) of said comparator (COMPi) of higher order and a third input (C) coupled to an intermediate tap of said voltage divider (Ra-Rb).

    Abstract translation: 一种闪存模数转换器，包括具有差分输出的一组比较器（COMPi），产生一个温度测量代码和一组三输入（A，B，C）逻辑或非门（NORj），用于校正所述 通过提供由多个分压器（Ra-Rb）构成的无源接口，每个连接在非反相输出端（Ra-Rb）之间，具有增强的抗噪声能力和减小的不精确性，特别是在比较器内发生亚稳态时的高转换速率 （COMPi）和所述存储体的高阶比较器（COMPi + 1）的反相输出（out_n）的输出（out_p） 所述存储体的对应逻辑或非门（NORj）具有耦合到所述各个比较器（COMPi-1）的反相输出（out_n）的第一输入（A），耦合到非反相输出（out_p）的第二输入（B） 的比较器（COMPi）和耦合到所述分压器（Ra-Rb）的中间抽头的第三输入端（C）。

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