公开(公告)号：EP1231712A2

公开(公告)日：2002-08-14

申请号：EP02075529.4

申请日：2002-02-07

Applicant: STMicroelectronics S.r.l.

Inventor： Filoramo, Pietro ,  Chiarillo, Tiziano

IPC: H03G7/08

CPC classification number: H03G7/08

Abstract: A variable gain amplifier is described which comprises a first device to which a first control signal (Vc, Vcl) is applied so that the gain (Ail, Ai) of an output signal (iout, io) of the first device (11, 22, Q45-Q48) with respect to a first input signal (in, il, ir) is a function of the exponential type of the first control signal (Vc, Vcl). The amplifier comprises a feedback network (25, Q51-Q58) connected between an output terminal and an input terminal of the first device (22, Q45-Q48) so as to assure that the gain (Ai) in decibel of the first device (22, Q45-Q48) is a linear function of the first control signal (Vcl).

Abstract translation: 描述了可变增益放大器，其包括施加第一控制信号（Vc，Vcl）的第一装置，使得第一装置（11,22）的输出信号（iout，io）的增益（Ail，Ai） ，Q45-Q48）相对于第一输入信号（in，il，ir）是第一控制信号（Vc，Vcl）的指数类型的函数。 放大器包括连接在第一装置（22，Q45-Q48）的输出端子和输入端子之间的反馈网络（25，Q51-Q58），以便确保第一装置的分贝的增益（Ai）（ 22，Q45-Q48）是第一控制信号（Vcl）的线性函数。

公开(公告)号：EP0998025A1

公开(公告)日：2000-05-03

申请号：EP98830657.7

申请日：1998-10-30

Applicant: STMicroelectronics S.r.l.

Inventor： Filoramo, Pietro ,  Palmisano, Giuseppe ,  Salerno, Raffaele

IPC: H03D7/14 ,  H03D7/16

CPC classification number: H03D7/165 ,  H03D7/1433 ,  H03D7/145 ,  H03D7/1458 ,  H03D7/18

Abstract: The present invention relates to a low-noise quadrature phase I-Q modulator for applications in radio frequency signal receivers, of the type comprising a pair of Gilbert cell input stages (4, 5) driven by a feed voltage line (Vcc) and receiving in input respective square wave command signals (W LO,I , V LO,Q ) coming from a local oscillator (LO). The modulator comprises a circuital block (2) with transistors (Q1a, Q2a; Q1b, Q2b) connected to each cell (4,5) and destined to carry out a voltage-current conversion of a signal (V RF ) in radio frequency received from the block (2) itself; such block (2) further comprises a single degeneration resistance (R E1 ).

Abstract translation: 本发明涉及用于射频信号接收机的低噪声正交相位IQ调制器，其类型包括由馈电电压线（Vcc）驱动并在输入端接收的一对吉尔伯特单元输入级（4,5） 来自本地振荡器（LO）的各个方波指令信号（WLO，I，VLO，Q）。 调制器包括具有连接到每个单元（4,5）的晶体管（Q1a，Q2a; Q1b，Q2b）的电路块（2），并且目的地在从射频接收的射频中执行信号（VRF）的电压 - 电流转换 块（2）本身; 这种块（2）还包括单个退化电阻（RE1）。

公开(公告)号：EP0993122A1

公开(公告)日：2000-04-12

申请号：EP98830586.8

申请日：1998-10-06

Applicant: STMicroelectronics S.r.l.

Inventor： Filoramo, Pietro ,  Cosentino, Gaetano

IPC: H03L7/10 ,  H03L7/189 ,  H03J5/02

CPC classification number: H03L7/189

Abstract: A method for reducing the settling time in PLL circuits, particularly for use in an RF transceiver, which comprise a phase comparator (2), a filter (4), a digital-analog converter (8) and an adder (5) which are suitable to produce in output a voltage (V c ) for controlling a voltage-controlled oscillator (6) provided by means of a varactor, characterized in that it comprises the steps of:

-- determining the dependency of the control voltage (V c ) of the voltage-controlled oscillator (6) on the frequency of a selected channel of a transmitter;
-- generating a law describing the variation of the output current (I DAC ) of said digital-analog converter (8) such that the voltage (V DAC ) obtained from the output current of the digital-analog converter, added to an output voltage (V f ) of said filter (4), is such as to keep said filter voltage (V f ) constant, in order to reduce the settling time of the PLL circuit as a selected channel varies.

Abstract translation: 一种用于减少PLL电路中的建立时间的方法，特别是用于RF收发器中的方法，其包括相位比较器（2），滤波器（4），数模转换器（8）和加法器（5） 适于在输出中产生用于控制由变容二极管提供的压控振荡器（6）的电压（Vc），其特征在于包括以下步骤：确定电压 - 电压的控制电压（Vc） 控制振荡器（6）在发射机的选定信道的频率上; 产生描述所述数模转换器（8）的输出电流（IDAC）的变化的定律，使得从数模转换器的输出电流获得的电压（VDAC）加到输出电压（Vf）上 所述滤波器（4）为了保持所述滤波器电压（Vf）恒定，以便随着所选择的信道变化而减小PLL电路的建立时间。